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[/] [or1k/] [tags/] [stable/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [dc_ram.v] - Rev 1766
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////////////////////////////////////////////////////////////////////// //// //// //// OR1200's DC RAMs //// //// //// //// This file is part of the OpenRISC 1200 project //// //// http://www.opencores.org/cores/or1k/ //// //// //// //// Description //// //// Instatiation of DC RAM blocks. //// //// //// //// To Do: //// //// - make it smaller and faster //// //// //// //// Author(s): //// //// - Damjan Lampret, lampret@opencores.org //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // CVS Revision History // // $Log: not supported by cvs2svn $ // Revision 1.1.1.1 2001/10/06 10:18:36 igorm // no message // // Revision 1.2 2001/08/09 13:39:33 lampret // Major clean-up. // // Revision 1.1 2001/07/20 00:46:03 lampret // Development version of RTL. Libraries are missing. // // // synopsys translate_off `include "timescale.v" // synopsys translate_on `include "defines.v" module dc_ram( // Reset and clock clk, rst, // Internal i/f addr, en, we, datain, dataout ); parameter dw = `OPERAND_WIDTH; parameter aw = 11; // // I/O // input clk; input rst; input [aw-1:0] addr; input en; input [3:0] we; input [dw-1:0] datain; output [dw-1:0] dataout; `ifdef OR1200_NO_DC // // Data cache not implemented // assign dataout = {dw{1'b0}}; `else // // Instantiation of RAM block 0 // generic_spram_2048x8 dc_ram0( .clk(clk), .rst(rst), .ce(en), .we(we[0]), .oe(1'b1), .addr(addr), .di(datain[7:0]), .do(dataout[7:0]) ); // // Instantiation of RAM block 1 // generic_spram_2048x8 dc_ram1( .clk(clk), .rst(rst), .ce(en), .we(we[1]), .oe(1'b1), .addr(addr), .di(datain[15:8]), .do(dataout[15:8]) ); // // Instantiation of RAM block 2 // generic_spram_2048x8 dc_ram2( .clk(clk), .rst(rst), .ce(en), .we(we[2]), .oe(1'b1), .addr(addr), .di(datain[23:16]), .do(dataout[23:16]) ); // // Instantiation of RAM block 3 // generic_spram_2048x8 dc_ram3( .clk(clk), .rst(rst), .ce(en), .we(we[3]), .oe(1'b1), .addr(addr), .di(datain[31:24]), .do(dataout[31:24]) ); `endif endmodule
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