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[/] [or1k/] [tags/] [stable/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [dmmu.v] - Rev 1766
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////////////////////////////////////////////////////////////////////// //// //// //// OR1200's Data MMU top level //// //// //// //// This file is part of the OpenRISC 1200 project //// //// http://www.opencores.org/cores/or1k/ //// //// //// //// Description //// //// Instantiation of all DMMU blocks. //// //// //// //// To Do: //// //// - make it smaller and faster //// //// //// //// Author(s): //// //// - Damjan Lampret, lampret@opencores.org //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // CVS Revision History // // $Log: not supported by cvs2svn $ // Revision 1.1.1.1 2001/10/06 10:18:36 igorm // no message // // Revision 1.1 2001/08/17 08:03:35 lampret // *** empty log message *** // // Revision 1.2 2001/07/22 03:31:53 lampret // Fixed RAM's oen bug. Cache bypass under development. // // Revision 1.1 2001/07/20 00:46:03 lampret // Development version of RTL. Libraries are missing. // // // synopsys translate_off `include "timescale.v" // synopsys translate_on `include "defines.v" // // Data MMU // module dmmu( // Rst and clk clk, rst, // LSU i/f dmmu_en, supv, dmmulsu_vaddr, dmmulsu_lsuop, dmmulsu_stall, // Except I/F dmmuexcept_miss, dmmuexcept_fault, // SPR access spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o, // DC i/f dcdmmu_paddr ); parameter dw = `OPERAND_WIDTH; parameter aw = `OPERAND_WIDTH; // // I/O // // // Clock and reset // input clk; input rst; // // LSU I/F // input dmmu_en; input supv; input [aw-1:0] dmmulsu_vaddr; input [`LSUOP_WIDTH-1:0] dmmulsu_lsuop; output dmmulsu_stall; // // Exception I/F // output dmmuexcept_miss; output dmmuexcept_fault; // // SPR access // input spr_cs; input spr_write; input [aw-1:0] spr_addr; input [31:0] spr_dat_i; output [31:0] spr_dat_o; // // DC I/F // output [aw-1:0] dcdmmu_paddr; // // Internal wires and regs // wire dtlb_spr_access; wire [31:13] dtlb_ppn; wire dtlb_hit; wire dtlb_uwe; wire dtlb_ure; wire dtlb_swe; wire dtlb_sre; wire [31:0] dtlb_dat_o; // // Implemented bits inside match and translate registers // // dtlbwYmrX: vpn 31-10 v 0 // dtlbwYtrX: ppn 31-10 uwe 9 ure 8 swe 7 sre 6 // // dtlb memory width: // 19 bits for ppn // 13 bits for vpn // 1 bit for valid // 4 bits for protection `ifdef OR1200_NO_DMMU // // Put all outputs in inactive state // assign dmmulsu_stall = 1'b0; assign dmmuexcept_miss = 1'b0; assign dmmuexcept_fault = 1'b0; assign spr_dat_o = 32'h00000000; assign dcdmmu_paddr = dmmulsu_vaddr; `else // // DTLB SPR access // // 0C00 - 0E00 dtlbmr w0-3 // 0C00 - 0C80 dtlbmr w0 // 0C00 - 0C40 dtlbmr w0 [63:0] // // 0E00 - 1000 dtlbtr w0-3 // 0E00 - 0E80 dtlbtr w0 // 0E00 - 0E40 dtlbtr w0 [63:0] // assign dtlb_spr_access = spr_cs & spr_addr[10]; // // Physical address is either translated virtual address or // simply equal when DMMU is disabled // assign dcdmmu_paddr = dmmu_en ? {dtlb_ppn, dmmulsu_vaddr[12:0]} : dmmulsu_vaddr; // // Output to SPRS unit // assign spr_dat_o = dtlb_spr_access ? dtlb_dat_o : 32'h00000000; // // DMMU stall // assign dmmulsu_stall = 1'b0; // // Page fault exception logic // assign dmmuexcept_fault = (|dmmulsu_lsuop) && dmmu_en && ( (!dmmulsu_lsuop[3] & !supv & !dtlb_ure) // Load in user mode not enabled || (!dmmulsu_lsuop[3] & supv & !dtlb_sre) // Load in supv mode not enabled || (dmmulsu_lsuop[3] & !supv & !dtlb_uwe) // Store in user mode not enabled || (dmmulsu_lsuop[3] & supv & !dtlb_swe) ); // Store in supv mode not enabled // // TLB Miss exception logic // assign dmmuexcept_miss = (|dmmulsu_lsuop) && dmmu_en && !dtlb_hit; // // Instantiation of DTLB // dtlb dtlb( // Rst and clk .clk(clk), .rst(rst), // I/F for translation .tlb_en(dmmu_en), .vaddr(dmmulsu_vaddr), .hit(dtlb_hit), .ppn(dtlb_ppn), .uwe(dtlb_uwe), .ure(dtlb_ure), .swe(dtlb_swe), .sre(dtlb_sre), // SPR access .spr_cs(dtlb_spr_access), .spr_write(spr_write), .spr_addr(spr_addr), .spr_dat_i(spr_dat_i), .spr_dat_o(dtlb_dat_o) ); `endif endmodule
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