URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
[/] [or1k/] [tags/] [stable/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [ic_fsm.v] - Rev 1766
Go to most recent revision | Compare with Previous | Blame | View Log
////////////////////////////////////////////////////////////////////// //// //// //// OR1200's IC FSM //// //// //// //// This file is part of the OpenRISC 1200 project //// //// http://www.opencores.org/cores/or1k/ //// //// //// //// Description //// //// Instruction cache state machine //// //// //// //// To Do: //// //// - make it smaller and faster //// //// //// //// Author(s): //// //// - Damjan Lampret, lampret@opencores.org //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // CVS Revision History // // $Log: not supported by cvs2svn $ // Revision 1.1.1.1 2001/10/06 10:18:36 igorm // no message // // Revision 1.3 2001/08/17 08:01:19 lampret // IC enable/disable. // // Revision 1.2 2001/08/09 13:39:33 lampret // Major clean-up. // // Revision 1.1 2001/07/20 00:46:03 lampret // Development version of RTL. Libraries are missing. // // // synopsys translate_off `include "timescale.v" // synopsys translate_on `include "defines.v" `define ICFSM_IDLE 3'd0 `define ICFSM_DOLOAD 3'd1 `define ICFSM_LREFILL3 3'd2 // // Insn cache FSM for cache line of 16 bytes (4x singleword) // module ic_fsm( // Clock and reset clk, rst, // Internal i/f fetch_op, miss, biudata_valid, start_addr, saved_addr, refill, refill_first, refill_prepare, icram_we, biu_read, refill_rest, cntrbusy ); // // I/O // input clk; input rst; input miss; input biudata_valid; input [31:0] start_addr; input [`FETCHOP_WIDTH-1:0] fetch_op; output [31:0] saved_addr; output refill; output refill_first; output refill_prepare; output [3:0] icram_we; output biu_read; output refill_rest; output cntrbusy; // // Internal wires and regs // wire icache_off = 1'b0; reg [31:0] saved_addr; reg refill; reg [3:0] icram_we; reg [2:0] state; reg [2:0] cnt; reg refill_first; reg refill_prepare; reg biu_read; reg refill_rest; reg cntrbusy; // // Generate ICRAM's write enable // always @(refill_first or refill or biudata_valid or fetch_op or start_addr) begin if (refill_first || !refill) case(fetch_op) `FETCHOP_LW : icram_we = 4'b0000 ^ {4{refill_first}}; default : icram_we = 4'b0000; endcase else icram_we = {4{refill & biudata_valid}}; end // // Main IC FSM // always @(posedge clk or posedge rst) begin if (rst) begin refill <= #1 1'b0; state <= #1 `ICFSM_IDLE; biu_read <= #1 1'b0; saved_addr <= #1 32'b0; refill_first <= #1 1'b0; refill_prepare <= #1 1'b0; refill_rest <= #1 1'b0; cntrbusy <= #1 1'b0; cnt <= #1 3'b0; end else case (state) // synopsys full_case parallel_case `ICFSM_IDLE : case(fetch_op) `FETCHOP_LW: begin `ifdef OR1200_VERBOSE // synopsys translate_off $display("%t: IC_FSM Load op %h start_addr %h", $time, fetch_op, start_addr); // synopsys translate_on `endif state <= #1 `ICFSM_DOLOAD; refill <= #1 1'b0; saved_addr <= #1 start_addr; refill_first <= #1 1'b0; refill_prepare <= #1 1'b1; biu_read <= #1 1'b0; refill_rest <= #1 1'b0; cntrbusy <= #1 1'b0; end default: begin state <= #1 `ICFSM_IDLE; refill <= #1 1'b0; refill_first <= #1 1'b0; refill_prepare <= #1 1'b0; refill_rest <= #1 1'b0; biu_read <= #1 1'b0; cntrbusy <= #1 1'b0; end endcase `ICFSM_DOLOAD: if (icache_off) begin `ifdef OR1200_VERBOSE // synopsys translate_off $display("%t: IC_FSM ICache off", $time); // synopsys translate_on `endif state <= #1 `ICFSM_DOLOAD; refill <= #1 1'b1; refill_first <= #1 1'b1; refill_prepare <= #1 1'b0; refill_rest <= #1 1'b0; biu_read <= #1 1'b1; if (biudata_valid) begin refill <= #1 1'b0; refill_first <= #1 1'b0; biu_read <= #1 1'b0; saved_addr <= #1 start_addr; end end else if (miss) begin `ifdef OR1200_VERBOSE // synopsys translate_off $display("%t: IC_FSM Load miss", $time); // synopsys translate_on `endif state <= #1 `ICFSM_LREFILL3; refill <= #1 1'b1; refill_first <= #1 1'b1; refill_prepare <= #1 1'b0; refill_rest <= #1 1'b0; cnt <= #1 3'd3; biu_read <= #1 1'b1; end else begin `ifdef OR1200_VERBOSE // synopsys translate_off $display("%t: IC_FSM Load hit", $time); // synopsys translate_on `endif state <= #1 `ICFSM_DOLOAD; saved_addr <= #1 start_addr; refill <= #1 1'b0; refill_first <= #1 1'b0; refill_prepare <= #1 1'b0; refill_rest <= #1 1'b0; cntrbusy <= #1 (fetch_op) ? 1'b1 : 1'b0; end `ICFSM_LREFILL3 : begin if (biudata_valid && cnt) begin `ifdef OR1200_VERBOSE // synopsys translate_off $display("%t: IC_FSM Load refill %d", $time, cnt); // synopsys translate_on `endif cnt <= #1 cnt - 'd1; saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1; refill_first <= #1 1'b0; end else if (biudata_valid) begin `ifdef OR1200_VERBOSE // synopsys translate_off $display("%t: IC_FSM Load refill end", $time, cnt); // synopsys translate_on `endif state <= #1 `ICFSM_DOLOAD; saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1; refill <= #1 1'b1; refill_first <= #1 1'b0; biu_read <= #1 1'b0; cntrbusy <= #1 (fetch_op) ? 1'b1 : 1'b0; end refill_rest <= #1 ~refill_first & refill; end endcase end endmodule
Go to most recent revision | Compare with Previous | Blame | View Log