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[/] [or1k/] [tags/] [stable/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [lsu.v] - Rev 1766
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////////////////////////////////////////////////////////////////////// //// //// //// OR1200's Load/Store unit //// //// //// //// This file is part of the OpenRISC 1200 project //// //// http://www.opencores.org/cores/or1k/ //// //// //// //// Description //// //// Interface between CPU and DC. //// //// //// //// To Do: //// //// - make it smaller and faster //// //// //// //// Author(s): //// //// - Damjan Lampret, lampret@opencores.org //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // CVS Revision History // // $Log: not supported by cvs2svn $ // Revision 1.1.1.1 2001/10/06 10:18:36 igorm // no message // // Revision 1.2 2001/08/09 13:39:33 lampret // Major clean-up. // // Revision 1.1 2001/07/20 00:46:03 lampret // Development version of RTL. Libraries are missing. // // // synopsys translate_off `include "timescale.v" // synopsys translate_on `include "defines.v" module lsu( // Clock and reset clk, rst, // Internal i/f addrbase, addrofs, lsu_op, lsu_datain, lsu_dataout, lsu_stall, // External i/f to DC dc_stall, dc_addr, dc_datain, dc_dataout, dc_lsuop ); parameter dw = `OPERAND_WIDTH; parameter aw = `REGFILE_ADDR_WIDTH; // // I/O // // // Clock and reset // input clk; input rst; // // Internal i/f // input [31:0] addrbase; input [31:0] addrofs; input [`LSUOP_WIDTH-1:0] lsu_op; input [dw-1:0] lsu_datain; output [dw-1:0] lsu_dataout; output lsu_stall; // // External i/f to DC // input dc_stall; output [31:0] dc_addr; input [dw-1:0] dc_datain; output [dw-1:0] dc_dataout; output [`LSUOP_WIDTH-1:0] dc_lsuop; // // Not much of a LSU right now // assign dc_addr = addrbase + addrofs; assign dc_dataout = lsu_datain; assign lsu_dataout = dc_datain; assign lsu_stall = dc_stall; assign dc_lsuop = lsu_op; endmodule
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