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[/] [or1k/] [tags/] [stable/] [mp3/] [rtl/] [verilog/] [or1200.xcv/] [reg2mem.v] - Rev 1766
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////////////////////////////////////////////////////////////////////// //// //// //// OR1200's reg2mem aligner //// //// //// //// This file is part of the OpenRISC 1200 project //// //// http://www.opencores.org/cores/or1k/ //// //// //// //// Description //// //// Aligns register data to memory alignment. //// //// //// //// To Do: //// //// - make it smaller and faster //// //// //// //// Author(s): //// //// - Damjan Lampret, lampret@opencores.org //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // CVS Revision History // // $Log: not supported by cvs2svn $ // Revision 1.1.1.1 2001/10/06 10:18:36 igorm // no message // // Revision 1.2 2001/08/09 13:39:33 lampret // Major clean-up. // // Revision 1.1 2001/07/20 00:46:21 lampret // Development version of RTL. Libraries are missing. // // // synopsys translate_off `include "timescale.v" // synopsys translate_on `include "defines.v" module reg2mem(addr, lsu_op, regdata, memdata); parameter width = `OPERAND_WIDTH; // // I/O // input [1:0] addr; input [`LSUOP_WIDTH-1:0] lsu_op; input [width-1:0] regdata; output [width-1:0] memdata; // // Internal regs and wires // reg [width-1:0] memdata; // // Mux to memdata[31:24] // always @(lsu_op or addr or regdata) begin casex({lsu_op, addr[1:0]}) // synopsys full_case parallel_case {`LSUOP_SB, 2'b00} : memdata[31:24] = regdata[7:0]; {`LSUOP_SH, 2'b00} : memdata[31:24] = regdata[15:8]; default : memdata[31:24] = regdata[31:24]; endcase end // // Mux to memdata[23:16] // always @(lsu_op or addr or regdata) begin casex({lsu_op, addr[1:0]}) // synopsys full_case parallel_case {`LSUOP_SW, 2'b00} : memdata[23:16] = regdata[23:16]; default : memdata[23:16] = regdata[7:0]; endcase end // // Mux to memdata[15:8] // always @(lsu_op or addr or regdata) begin casex({lsu_op, addr[1:0]}) // synopsys full_case parallel_case {`LSUOP_SB, 2'b10} : memdata[15:8] = regdata[7:0]; default : memdata[15:8] = regdata[15:8]; endcase end // // Mux to memdata[7:0] // always @(regdata) memdata[7:0] = regdata[7:0]; endmodule
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