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[/] [or1k/] [tags/] [stable_0_1_0/] [or1ksim/] [peripheral/] [mc.c] - Rev 261
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/* mc.c -- Simulation of Memory Controller Copyright (C) 2001 by Marko Mlinar, markom@opencores.org This file is part of OpenRISC 1000 Architectural Simulator. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ /* Enable memory controller, via: section mc enable = 1 POC = 0x13243545 end Limitations: - memory refresh is not simulated */ #include "mc.h" #include "abstract.h" #include "sim-config.h" static struct mc mc; void set_csc_tms (int i, unsigned long csc, unsigned long tms) { if (1); } /* Set a specific MC register with value. */ void mc_write_word(unsigned long addr, unsigned long value) { int chipsel; debug("mc_write_word(%x,%08x)\n", addr, (unsigned)value); addr -= config.mc.baseaddr; switch (addr) { case MC_CSR: mc.csr = value; break; case MC_POC: fprintf (stderr, "warning: write to MC's POC register!"); break; case MC_BA_MASK: mc.ba_mask = value; break; default: if (addr >= MC_CSC(0) && addr <= MC_TMS(N_CE - 1)) { addr -= MC_CSC(0); if ((addr >> 2) & 1) mc.tms[addr >> 3] = value; else mc.csc[addr >> 3] = value; set_csc_tms (addr >> 3, mc.csc[addr >> 3], mc.tms[addr >> 3]); break; } else debug("write out of range (addr %x)\n", addr + config.mc.baseaddr); } } /* Read a specific MC register. */ unsigned long mc_read_word(unsigned long addr) { unsigned char value = 0; int chipsel; debug("mc_read_word(%x)\n", addr); addr -= config.mc.baseaddr; switch (addr) { case MC_CSR: value = mc.csr; break; case MC_POC: value = mc.poc; break; case MC_BA_MASK: value = mc.ba_mask; break; default: if (addr >= MC_CSC(0) && addr <= MC_TMS(N_CE - 1)) { addr -= MC_CSC(0); if ((addr >> 2) & 1) value = mc.tms[addr >> 3]; else value = mc.csc[addr >> 3]; } else debug("read out of range (addr %x)\n", addr + config.mc.baseaddr); break; } return value; } /* Read POC register and init memory controler regs. */ void mc_reset() { if (config.mc.enabled) { printf("Resetting memory controller.\n"); memset(&mc, 0, sizeof(struct mc)); mc.poc = config.mc.POC; register_memoryarea(config.mc.baseaddr, MC_ADDR_SPACE, 4, mc_read_word, mc_write_word); } } inline void mc_clock() { }
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