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[/] [or1k/] [tags/] [stable_0_2_0_rc2/] [or1ksim/] [cpu/] [or1k/] [sprs.c] - Rev 1404
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/* sprs.c -- Simulation of OR1K special-purpose registers Copyright (C) 1999 Damjan Lampret, lampret@opencores.org This file is part of OpenRISC 1000 Architectural Simulator. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include <stdlib.h> #include <stdio.h> #include <string.h> #include <errno.h> #include "config.h" #ifdef HAVE_INTTYPES_H #include <inttypes.h> #endif #include "port.h" #include "arch.h" #include "abstract.h" #include "sprs.h" #include "sim-config.h" #include "except.h" #include "execute.h" #include "dcache_model.h" #include "icache_model.h" extern int flag; sprword sprs[MAX_SPRS]; int audio_cnt = 0; static FILE *fo = 0; /* Set a specific SPR with a value. */ inline void mtspr(uint16_t regno, const sprword value) { regno %= MAX_SPRS; sprs[regno] = value; /* MM: Register hooks. */ switch (regno) { case SPR_TTCR: spr_write_ttcr (value); break; case SPR_TTMR: spr_write_ttmr (value); break; /* Data cache simulateing stuff */ case SPR_DCBPR: if(value) { dc_simulate_read(value, 4); sprs[SPR_DCBPR] = 0; } break; case SPR_DCBFR: if(value != -1) { dc_inv(value); sprs[SPR_DCBFR] = -1; } break; case SPR_DCBIR: if(value != 0) { dc_inv(value); sprs[SPR_DCBIR] = 0; } break; case SPR_DCBWR: sprs[SPR_DCBWR] = 0; break; case SPR_DCBLR: sprs[SPR_DCBLR] = 0; break; /* Instruction cache simulateing stuff */ case SPR_ICBPR: if(value) { ic_simulate_fetch(value); sprs[SPR_ICBPR] = 0; } break; case SPR_ICBIR: if(value) { ic_inv(value); sprs[SPR_ICBIR] = 0; } break; case SPR_ICBLR: sprs[SPR_ICBLR] = 0; break; case SPR_SR: /* Set internal flag also */ if(value & SPR_SR_F) flag = 1; else flag = 0; sprs[regno] |= SPR_SR_FO; break; case SPR_NPC: { extern int delay_insn; /* The debugger has redirected us to a new address */ /* This is usually done to reissue an instruction which just caused a breakpoint exception. */ pc = value; if(!value && config.sim.verbose) PRINTF("WARNING: PC just set to 0!\n"); /* Clear any pending delay slot jumps also */ delay_insn = 0; pcnext = value + 4; } break; case 0xFFFD: fo = fopen ("audiosim.pcm", "wb+"); if (!fo) PRINTF("Cannot open audiosim.pcm\n"); PRINTF("Audio opened.\n"); break; case 0xFFFE: if (!fo) PRINTF("audiosim.pcm not opened\n"); fputc (value & 0xFF, fo); if ((audio_cnt % 1024) == 0) PRINTF("%i\n", audio_cnt); audio_cnt++; break; case 0xFFFF: fclose(fo); PRINTF("Audio closed.\n"); runtime.sim.cont_run = 0; break; case SPR_PMR: /* PMR[SDF] and PMR[DCGE] are ignored completely. */ if (value & SPR_PMR_SUME) { PRINTF ("SUSPEND: PMR[SUME] bit was set.\n"); runtime.sim.cont_run = 0; } break; default: /* Mask reseved bits in DTLBMR and DTLBMR registers */ if ( (regno >= SPR_DTLBMR_BASE(0)) && (regno < SPR_DTLBTR_LAST(3))) { if((regno & 0xff) < 0x80) sprs[regno] = ((value / config.dmmu.pagesize) * config.dmmu.pagesize) | (value & (SPR_DTLBMR_V | SPR_DTLBMR_PL1 | SPR_DTLBMR_CID | SPR_DTLBMR_LRU)); else sprs[regno] = ((value / config.dmmu.pagesize) * config.dmmu.pagesize) | (value & (SPR_DTLBTR_CC | SPR_DTLBTR_CI | SPR_DTLBTR_WBC | SPR_DTLBTR_WOM | SPR_DTLBTR_A | SPR_DTLBTR_D | SPR_DTLBTR_URE | SPR_DTLBTR_UWE | SPR_DTLBTR_SRE | SPR_DTLBTR_SWE)); } /* Mask reseved bits in ITLBMR and ITLBMR registers */ if ( (regno >= SPR_ITLBMR_BASE(0)) && (regno < SPR_ITLBTR_LAST(3))) { if((regno & 0xff) < 0x80) sprs[regno] = ((value / config.immu.pagesize) * config.immu.pagesize) | (value & (SPR_ITLBMR_V | SPR_ITLBMR_PL1 | SPR_ITLBMR_CID | SPR_ITLBMR_LRU)); else sprs[regno] = ((value / config.immu.pagesize) * config.immu.pagesize) | (value & (SPR_ITLBTR_CC | SPR_ITLBTR_CI | SPR_ITLBTR_WBC | SPR_ITLBTR_WOM | SPR_ITLBTR_A | SPR_ITLBTR_D | SPR_ITLBTR_SXE | SPR_ITLBTR_UXE)); } /* Links to GPRS */ if(regno >= 0x0400 && regno < 0x0420) { extern uorreg_t reg[32]; reg[regno - 0x0400] = value; } break; } } /* Show status of important SPRs. */ void sprs_status() { PRINTF("VR : 0x%.8lx UPR : 0x%.8lx\n", mfspr(SPR_VR), mfspr(SPR_UPR)); PRINTF("SR : 0x%.8lx\n", mfspr(SPR_SR)); PRINTF("MACLO: 0x%.8lx MACHI: 0x%.8lx\n", mfspr(SPR_MACLO), mfspr(SPR_MACHI)); PRINTF("EPCR0: 0x%.8lx EPCR1: 0x%.8lx\n", mfspr(SPR_EPCR_BASE), mfspr(SPR_EPCR_BASE+1)); PRINTF("EEAR0: 0x%.8lx EEAR1: 0x%.8lx\n", mfspr(SPR_EEAR_BASE), mfspr(SPR_EEAR_BASE+1)); PRINTF("ESR0 : 0x%.8lx ESR1 : 0x%.8lx\n", mfspr(SPR_ESR_BASE), mfspr(SPR_ESR_BASE+1)); PRINTF("TTMR : 0x%.8lx TTCR : 0x%.8lx\n", mfspr(SPR_TTMR), mfspr(SPR_TTCR)); PRINTF("PICMR: 0x%.8lx PICSR: 0x%.8lx\n", mfspr(SPR_PICMR), mfspr(SPR_PICSR)); PRINTF("PPC: 0x%.8lx NPC : 0x%.8lx\n", mfspr(SPR_PPC), mfspr(SPR_NPC)); }
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