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[/] [or1k/] [tags/] [tn_m001/] [or1ksim/] [testbench/] [except_test.cfg] - Rev 730

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section memory
  /*random_seed = 12345
  type = random*/
  pattern = 0x00
  type = unknown /* Fastest */

  nmemories = 3
  device 0
    name = "RAM1"
    ce = 0
    baseaddr = 0x40000000
    size = 0x00200000
    delayr = 1
    delayw = 2
  enddevice

  device 1
    name = "FLASH"
    ce = 1
    baseaddr = 0x00000000
    size = 0x00200000
    delayr = 10
    delayw = -1
  enddevice

  device 2
    name = "RAM2"
    ce = 2
    baseaddr = 0x80000000
    size = 0x00200000
    delayr = 1
    delayw = 2
  enddevice
end

section immu
  enabled = 1
  nsets = 32
  nways = 1
  pagesize = 8192
end

section dmmu
  enabled = 1
  nsets = 32
  nways = 1
  pagesize = 8192
end

section ic
  enabled = 0
  nsets = 512
  nways = 1
  blocksize = 16
end

section dc
  enabled = 0
  nsets = 512
  nways = 1
  blocksize = 16
end

section sim
  history = 1
  exe_log = 1
  exe_log_fn = "executed.log"
  clkcycle = 4ns
end

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