URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
[/] [or1k/] [trunk/] [gdb-5.3/] [sim/] [testsuite/] [sim/] [fr30/] [and.cgs] - Rev 1773
Go to most recent revision | Compare with Previous | Blame | View Log
# fr30 testcase for and $Rj,$Ri, and $Rj,@$Ri
# mach(): fr30
.include "testutils.inc"
START
.text
.global and
and:
; Test and $Rj,$Ri
mvi_h_gr 0xaaaaaaaa,r7
mvi_h_gr 0x55555555,r8
set_cc 0x0b ; Set mask opposite of expected
and r7,r8
test_cc 0 1 1 1
test_h_gr 0,r8
mvi_h_gr 0xffff0000,r8
set_cc 0x04 ; Set mask opposite of expected
and r7,r8
test_cc 1 0 0 0
test_h_gr 0xaaaa0000,r8
mvi_h_gr 0xffff,r8
set_cc 0x0d ; Set mask opposite of expected
and r7,r8
test_cc 0 0 0 1
test_h_gr 0xaaaa,r8
; Test and $Rj,@$Ri
mvi_h_gr 0xaaaaaaaa,r7
mvi_h_mem 0x55555555,sp
set_cc 0x0b ; Set mask opposite of expected
and r7,@sp
test_cc 0 1 1 1
test_h_mem 0,sp
mvi_h_mem 0xffff0000,sp
set_cc 0x04 ; Set mask opposite of expected
and r7,@sp
test_cc 1 0 0 0
test_h_mem 0xaaaa0000,sp
mvr_h_gr sp,r9
inci_h_gr 4,r9
mvi_h_mem 0xffffffff,sp
mvi_h_mem 0xffff0000,r9
inci_h_gr 1,sp ; test unaligned access
set_cc 0x05 ; Set mask opposite of expected
and r7,@sp
test_cc 1 0 0 1
inci_h_gr -1,sp
test_h_mem 0xaaaaaaaa,sp
test_h_mem 0xffff0000,r9
pass
Go to most recent revision | Compare with Previous | Blame | View Log