Subversion Repositories or1k

 
\begin{document}
\vspace{50mm}\section{OpenRISC 1000 Instruction Set}
Draft, Do not distribute
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.illegal}&
\multicolumn{1}{c}{\textbf{\huge Illegal instruction}}&
\textbf{\huge l.illegal}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccccccccccccccccccccccccccc|}
\hline
31&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
0\\
\hline
\multicolumn{32}{|c|}{opcode 0x0}\\
 
\hline
\multicolumn{32}{|c|}{32 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.illegal\ }{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large The result of this instruction is always an illegal instruction exception.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
PC <- address of illegal instruction exception handler
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.j}&
\multicolumn{1}{c}{\textbf{\huge Jump}}&
\textbf{\huge l.j}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccc|cccccccccccccccccccccccccc|}
\hline
31&
&
&
&
&
26&
25&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
0\\
\hline
\multicolumn{6}{|c|}{opcode 0x0}&
\multicolumn{26}{c|}{X}\\
 
\hline
\multicolumn{6}{|c|}{6 bits}&
\multicolumn{26}{c|}{26 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.j\ X}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large The immediate is shifted left two bits, sign-extended to 32 bits and then added to the address of the delay slot. The result is effective address of the jump. The program unconditionally jumps to EA with a delay of one 32 bit or two 16 bit instructions.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
PC <- (Immediate || 00) + DelayInsnAddr\\LR <- DelayInsnAddr + 4
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.jal}&
\multicolumn{1}{c}{\textbf{\huge Jump and Link}}&
\textbf{\huge l.jal}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccc|cccccccccccccccccccccccccc|}
\hline
31&
&
&
&
&
26&
25&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
0\\
\hline
\multicolumn{6}{|c|}{opcode 0x1}&
\multicolumn{26}{c|}{X}\\
 
\hline
\multicolumn{6}{|c|}{6 bits}&
\multicolumn{26}{c|}{26 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.jal\ X}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large The immediate is shifted left two bits, sign-extended to 32 bits and then added to the address of the delay slot. The result is effective address of the jump. The program unconditionally jumps to EA with a delay of one 32 bit or two 16 bit instructions. The address of the instruction after the delay slot is placed in the link register. }{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
PC <- (Immediate || 00) + DelayInsnAddr\\LR <- DelayInsnAddr + 4
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.bnf}&
\multicolumn{1}{c}{\textbf{\huge Branch if No Flag}}&
\textbf{\huge l.bnf}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccc|cccccccccccccccccccccccccc|}
\hline
31&
&
&
&
&
26&
25&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
0\\
\hline
\multicolumn{6}{|c|}{opcode 0x2}&
\multicolumn{26}{c|}{X}\\
 
\hline
\multicolumn{6}{|c|}{6 bits}&
\multicolumn{26}{c|}{26 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.bnf\ X}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large The immediate is shifted left two bits, sign-extended to 32 bits and then added to the address of the delay slot. The result is effective address of the branch. If the compare flag is cleared, then the program branches to EA with a delay of one 32 bit or two 16 bit instructions.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
EA <- (Immediate || 00) + DelayInsnAddr\\PC <- EA if flag cleared
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.bf}&
\multicolumn{1}{c}{\textbf{\huge Branch if Flag}}&
\textbf{\huge l.bf}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccc|cccccccccccccccccccccccccc|}
\hline
31&
&
&
&
&
26&
25&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
0\\
\hline
\multicolumn{6}{|c|}{opcode 0x3}&
\multicolumn{26}{c|}{X}\\
 
\hline
\multicolumn{6}{|c|}{6 bits}&
\multicolumn{26}{c|}{26 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.bf\ X}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large The immediate is shifted left two bits, sign-extended to 32 bits and then added to the address of the delay slot. The result is effective address of the branch. If the compare flag is set, then the program branches to EA with a delay of one 32 bit or two 16 bit instructions.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
EA <- (Immediate || 00) + DelayInsnAddr\\PC <- EA if flag set
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.load32u}&
\multicolumn{1}{c}{\textbf{\huge Load Word and Extend with Zero}}&
\textbf{\huge l.load32u}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|ccccccc|c|cccc|cccc|cccccccccccccccc|}
\hline
31&
&
&
&
&
&
25&
24&
23&
&
&
20&
19&
&
&
16&
15&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
0\\
\hline
\multicolumn{7}{|c|}{opcode 0x8}&
\multicolumn{1}{c|}{J}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}&
\multicolumn{16}{c|}{J}\\
 
\hline
\multicolumn{7}{|c|}{7 bits}&
\multicolumn{1}{c|}{1 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{16}{c|}{16 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.load32u\ rA,J(rB)}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large Offset is sign-extended and added to the contents of general register rB. Sum represents effective address. The word in memory addressed by EA is loaded into general register rA. }{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
EA <- exts(Immediate) + rB\\rA <- (EA){[}31:0{]}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.load16u}&
\multicolumn{1}{c}{\textbf{\huge Load Half Word and Extend with Zero}}&
\textbf{\huge l.load16u}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|ccccccc|c|cccc|cccc|cccccccccccccccc|}
\hline
31&
&
&
&
&
&
25&
24&
23&
&
&
20&
19&
&
&
16&
15&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
0\\
\hline
\multicolumn{7}{|c|}{opcode 0x9}&
\multicolumn{1}{c|}{J}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}&
\multicolumn{16}{c|}{J}\\
 
\hline
\multicolumn{7}{|c|}{7 bits}&
\multicolumn{1}{c|}{1 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{16}{c|}{16 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.load16u\ rA,J(rB)}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large Offset is sign-extended and added to the contents of general register rB. Sum represents effective address. The half word in memory addressed by EA is loaded into the low-order 16 bits of general register rA. High-order 16 bits of general register rA are replaced with zero.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
EA <- exts(Immediate) + rB\\rA{[}15:0{]} <- (EA){[}15:0{]}\\rA{[}31:16{]} <- 0
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.load16s}&
\multicolumn{1}{c}{\textbf{\huge Load Half Word and Extend with Sign}}&
\textbf{\huge l.load16s}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|ccccccc|c|cccc|cccc|cccccccccccccccc|}
\hline
31&
&
&
&
&
&
25&
24&
23&
&
&
20&
19&
&
&
16&
15&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
0\\
\hline
\multicolumn{7}{|c|}{opcode 0xa}&
\multicolumn{1}{c|}{J}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}&
\multicolumn{16}{c|}{J}\\
 
\hline
\multicolumn{7}{|c|}{7 bits}&
\multicolumn{1}{c|}{1 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{16}{c|}{16 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.load16s\ rA,J(rB)}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large Offset is sign-extended and added to the contents of general register rB. Sum represents effective address. The half word in memory addressed by EA is loaded into the low-order 16 bits of general register rA. High-order 16 bits of general register rA are replaced with bit 15 of the loaded value.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
EA <- exts(Immediate) + rB\\rA{[}15:0{]} <- (EA){[}15:0{]}\\rA{[}31:16{]} <- rA{[}15{]}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.load8u}&
\multicolumn{1}{c}{\textbf{\huge Load Byte and Extend with Zero}}&
\textbf{\huge l.load8u}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|ccccccc|c|cccc|cccc|cccccccccccccccc|}
\hline
31&
&
&
&
&
&
25&
24&
23&
&
&
20&
19&
&
&
16&
15&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
0\\
\hline
\multicolumn{7}{|c|}{opcode 0xb}&
\multicolumn{1}{c|}{J}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}&
\multicolumn{16}{c|}{J}\\
 
\hline
\multicolumn{7}{|c|}{7 bits}&
\multicolumn{1}{c|}{1 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{16}{c|}{16 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.load8u\ rA,J(rB)}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large Offset is sign-extended and added to the contents of general register rB. Sum represents effective address. The byte in memory addressed by EA is loaded into the low-order eight bits of general register rA. High-order 24 bits of general register rA are replaced with zero.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
EA <- exts(Immediate) + rB\\rA{[}7:0{]} <- (EA){[}7:0{]}\\rA{[}31:8{]} <- 0
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.load8s}&
\multicolumn{1}{c}{\textbf{\huge Load Byte and Extend with Sign}}&
\textbf{\huge l.load8s}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|ccccccc|c|cccc|cccc|cccccccccccccccc|}
\hline
31&
&
&
&
&
&
25&
24&
23&
&
&
20&
19&
&
&
16&
15&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
0\\
\hline
\multicolumn{7}{|c|}{opcode 0xc}&
\multicolumn{1}{c|}{J}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}&
\multicolumn{16}{c|}{J}\\
 
\hline
\multicolumn{7}{|c|}{7 bits}&
\multicolumn{1}{c|}{1 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{16}{c|}{16 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.load8s\ rA,J(rB)}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large Offset is sign-extended and added to the contents of general register rB. Sum represents effective address. The byte in memory addressed by EA is loaded into the low-order eight bits of general register rA. High-order 24 bits of general register rA are replaced with bit 7 of the loaded value.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
EA <- exts(Immediate) + rB\\rA{[}7:0{]} <- (EA){[}7:0{]}\\rA{[}31:8{]} <- rA{[}8{]}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.stor32}&
\multicolumn{1}{c}{\textbf{\huge Store Word}}&
\textbf{\huge l.stor32}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|ccccccc|c|cccc|cccc|cccccccccccccccc|}
\hline
31&
&
&
&
&
&
25&
24&
23&
&
&
20&
19&
&
&
16&
15&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
0\\
\hline
\multicolumn{7}{|c|}{opcode 0xd}&
\multicolumn{1}{c|}{J}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}&
\multicolumn{16}{c|}{J}\\
 
\hline
\multicolumn{7}{|c|}{7 bits}&
\multicolumn{1}{c|}{1 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{16}{c|}{16 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.stor32\ J(rA),rB}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large Offset is sign-extended and added to the contents of general register rA. Sum represents effective address. The word in general register rB is stored to memory addressed by EA. }{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
EA <- exts(Immediate) + rA\\(EA){[}31:0{]} <- rB
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.stor16}&
\multicolumn{1}{c}{\textbf{\huge Store Half Word}}&
\textbf{\huge l.stor16}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|ccccccc|c|cccc|cccc|cccccccccccccccc|}
\hline
31&
&
&
&
&
&
25&
24&
23&
&
&
20&
19&
&
&
16&
15&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
0\\
\hline
\multicolumn{7}{|c|}{opcode 0xe}&
\multicolumn{1}{c|}{J}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}&
\multicolumn{16}{c|}{J}\\
 
\hline
\multicolumn{7}{|c|}{7 bits}&
\multicolumn{1}{c|}{1 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{16}{c|}{16 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.stor16\ J(rA),rB}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large Offset is sign-extended and added to the contents of general register rA. Sum represents effective address. The low-order 16 bits of general register rB are stored to memory addressed by EA. }{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
EA <- exts(Immediate) + rA\\(EA){[}15:0{]} <- rB{[}15:0{]}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.stor8}&
\multicolumn{1}{c}{\textbf{\huge Store Byte}}&
\textbf{\huge l.stor8}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|ccccccc|c|cccc|cccc|cccccccccccccccc|}
\hline
31&
&
&
&
&
&
25&
24&
23&
&
&
20&
19&
&
&
16&
15&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
0\\
\hline
\multicolumn{7}{|c|}{opcode 0xf}&
\multicolumn{1}{c|}{J}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}&
\multicolumn{16}{c|}{J}\\
 
\hline
\multicolumn{7}{|c|}{7 bits}&
\multicolumn{1}{c|}{1 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{16}{c|}{16 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.stor8\ J(rA),rB}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large Offset is sign-extended and added to the contents of general register rA. Sum represents effective address. The low-order 8 bits of general register rB are stored to memory addressed by EA. }{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
EA <- exts(Immediate) + rA\\(EA){[}7:0{]} <- rB{[}7:0{]}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.addi32s}&
\multicolumn{1}{c}{\textbf{\huge Add Immediate Signed}}&
\textbf{\huge l.addi32s}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccc|cc|cccc|cccc|cccccccccccccccc|}
\hline
31&
&
&
&
&
26&
25&
24&
23&
&
&
20&
19&
&
&
16&
15&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
0\\
\hline
\multicolumn{6}{|c|}{opcode 0x8}&
\multicolumn{2}{c|}{I}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}&
\multicolumn{16}{c|}{I}\\
 
\hline
\multicolumn{6}{|c|}{6 bits}&
\multicolumn{2}{c|}{2 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{16}{c|}{16 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.addi32s\ rA,rB,I}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large Immediate is signed-extended and added to the contents of general register rB to form the result. The result is placed into general register rA.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
rA <- rB + exts(Immediate)
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.subi32s}&
\multicolumn{1}{c}{\textbf{\huge Subtract Immediate Signed}}&
\textbf{\huge l.subi32s}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccc|cc|cccc|cccc|cccccccccccccccc|}
\hline
31&
&
&
&
&
26&
25&
24&
23&
&
&
20&
19&
&
&
16&
15&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
0\\
\hline
\multicolumn{6}{|c|}{opcode 0x9}&
\multicolumn{2}{c|}{I}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}&
\multicolumn{16}{c|}{I}\\
 
\hline
\multicolumn{6}{|c|}{6 bits}&
\multicolumn{2}{c|}{2 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{16}{c|}{16 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.subi32s\ rA,rB,I}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large Immediate is signed-extended and subtracted from the contents of general register rB to form the result. The result is placed into general register rA.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
rA <- rB - exts(Immediate)
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.muli32s}&
\multicolumn{1}{c}{\textbf{\huge Multiply Immediate Signed}}&
\textbf{\huge l.muli32s}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccccccccccccccc|}
\hline
31&
&
&
&
&
&
&
24&
23&
&
&
20&
19&
&
&
16&
15&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x28}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}&
\multicolumn{16}{c|}{I}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{16}{c|}{16 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.muli32s\ rA,rB,I}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large Immediate and the contents of general register rB are multiplied and the result is truncated to 32 bits and placed into general register rA.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
rA <- rB * Immediate
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 2: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Recommended\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.xori16}&
\multicolumn{1}{c}{\textbf{\huge Exclusive Or Immediate Half Word}}&
\textbf{\huge l.xori16}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccccccccccccccc|}
\hline
31&
&
&
&
&
&
&
24&
23&
&
&
20&
19&
&
&
16&
15&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x29}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}&
\multicolumn{16}{c|}{I}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{16}{c|}{16 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.xori16\ rA,rB,I}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large Immediate is zero-extended and combined with the contents of general register rB in a bit-wise logical XOR operation. The result is placed into general register rA.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
rA <- rB XOR exts(Immediate)
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 3: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Optional\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.immlo16u}&
\multicolumn{1}{c}{\textbf{\huge Immediate Low-Order Half Word Unsigned}}&
\textbf{\huge l.immlo16u}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccccccccccccccc|}
\hline
31&
&
&
&
&
&
&
24&
23&
&
&
20&
19&
&
&
16&
15&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x2a}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{reserved}&
\multicolumn{16}{c|}{I}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{16}{c|}{16 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.immlo16u\ rA,I}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large 16 bit immediate is placed into low-order 16 bits of general register rA.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
rA{[}15:0{]} <- Immediate
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.immhi16u}&
\multicolumn{1}{c}{\textbf{\huge Immediate High-Order Half Word Unsigned}}&
\textbf{\huge l.immhi16u}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccccccccccccccc|}
\hline
31&
&
&
&
&
&
&
24&
23&
&
&
20&
19&
&
&
16&
15&
&
&
&
&
&
&
&
&
&
&
&
&
&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x2b}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{reserved}&
\multicolumn{16}{c|}{I}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{16}{c|}{16 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.immhi16u\ rA,I}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large 16 bit immediate is placed into high-order 16 bits of general register rA.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
rA{[}31:16{]} <- Immediate
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.sub32s}&
\multicolumn{1}{c}{\textbf{\huge Subtract Signed}}&
\textbf{\huge l.sub32s}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccc|cccc|cccccccc|}
\hline
31&
&
&
&
&
&
&
24&
23&
&
&
20&
19&
&
&
16&
15&
&
&
12&
11&
&
&
8&
7&
&
&
&
&
&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x2c}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}&
\multicolumn{4}{c|}{C}&
\multicolumn{4}{c|}{opcode 0x0}&
\multicolumn{8}{c|}{reserved}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{8}{c|}{8 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.sub32s\ rA,rB,rC}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large The contents of general register rC is subtracted from the contents of general register rB to form the result. The result is placed into general register rA.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
rA <- rB - rC
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.shla32}&
\multicolumn{1}{c}{\textbf{\huge Shift Left Arithmetic}}&
\textbf{\huge l.shla32}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccc|cccc|ccccc|ccc|}
\hline
31&
&
&
&
&
&
&
24&
23&
&
&
20&
19&
&
&
16&
15&
&
&
12&
11&
&
&
8&
7&
&
&
&
3&
2&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x2c}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}&
\multicolumn{4}{c|}{C}&
\multicolumn{4}{c|}{opcode 0x1}&
\multicolumn{5}{c|}{L}&
\multicolumn{3}{c|}{reserved}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{5}{c|}{5 bits}&
\multicolumn{3}{c|}{3 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.shla32\ rA,rB,rC,L}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large Immediate is combined with low-order 5 bits of general register rC in a bit-wise logical OR operation. The result specifies the number of bit positions the contents of general register rB are shifted left, inserting zeros into the low-order bits.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
b <- Immediate | rC\\rA{[}31:b{]} <- rB{[}31-b:0{]}\\rA{[}b:0{]} <- 0
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.shra32}&
\multicolumn{1}{c}{\textbf{\huge Shift Right Arithmetic}}&
\textbf{\huge l.shra32}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccc|cccc|ccccc|ccc|}
\hline
31&
&
&
&
&
&
&
24&
23&
&
&
20&
19&
&
&
16&
15&
&
&
12&
11&
&
&
8&
7&
&
&
&
3&
2&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x2c}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}&
\multicolumn{4}{c|}{C}&
\multicolumn{4}{c|}{opcode 0x2}&
\multicolumn{5}{c|}{L}&
\multicolumn{3}{c|}{reserved}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{5}{c|}{5 bits}&
\multicolumn{3}{c|}{3 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.shra32\ rA,rB,rC,L}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large Immediate is combined with low-order 5 bits of general register rC in a bit-wise logical OR operation. The result specifies the number of bit positions the contents of general register rB are shifted right, sign-extending the high-order bits.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
b <- Immediate | rC\\rA{[}31-b:0{]} <- rB{[}31:b{]}\\rA{[}31-b:31{]} <- rB{[}31{]}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.shrl32}&
\multicolumn{1}{c}{\textbf{\huge Shift Right Logical}}&
\textbf{\huge l.shrl32}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccc|cccc|ccccc|ccc|}
\hline
31&
&
&
&
&
&
&
24&
23&
&
&
20&
19&
&
&
16&
15&
&
&
12&
11&
&
&
8&
7&
&
&
&
3&
2&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x2c}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}&
\multicolumn{4}{c|}{C}&
\multicolumn{4}{c|}{opcode 0x3}&
\multicolumn{5}{c|}{L}&
\multicolumn{3}{c|}{reserved}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{5}{c|}{5 bits}&
\multicolumn{3}{c|}{3 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.shrl32\ rA,rB,rC,L}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large Immediate is combined with low-order 5 bits of general register rC in a bit-wise logical OR operation. The result specifies the number of bit positions the contents of general register rB are shifted right, inserting zeros into the high-order bits.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
b <- Immediate | rC\\rA{[}31-b:0{]} <- rB{[}31:b{]}\\rA{[}31-b:31{]} <- 0
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.and32}&
\multicolumn{1}{c}{\textbf{\huge And}}&
\textbf{\huge l.and32}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccc|cccc|cccccccc|}
\hline
31&
&
&
&
&
&
&
24&
23&
&
&
20&
19&
&
&
16&
15&
&
&
12&
11&
&
&
8&
7&
&
&
&
&
&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x2c}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}&
\multicolumn{4}{c|}{C}&
\multicolumn{4}{c|}{opcode 0x4}&
\multicolumn{8}{c|}{reserved}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{8}{c|}{8 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.and32\ rA,rB,rC}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large The contents of general register rB are combined with the contents of general register rC in a bit-wise logical AND operation. The result is placed into general register rA.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
rA <- rB AND rC
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.or32}&
\multicolumn{1}{c}{\textbf{\huge Or}}&
\textbf{\huge l.or32}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccc|cccc|cccccccc|}
\hline
31&
&
&
&
&
&
&
24&
23&
&
&
20&
19&
&
&
16&
15&
&
&
12&
11&
&
&
8&
7&
&
&
&
&
&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x2c}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}&
\multicolumn{4}{c|}{C}&
\multicolumn{4}{c|}{opcode 0x5}&
\multicolumn{8}{c|}{reserved}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{8}{c|}{8 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.or32\ rA,rB,rC}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large The contents of general register rB are combined with the contents of general register rC in a bit-wise logical OR operation. The result is placed into general register rA.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
rA <- rB OR rC
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.xor32}&
\multicolumn{1}{c}{\textbf{\huge Exclusive Or}}&
\textbf{\huge l.xor32}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccc|cccc|cccccccc|}
\hline
31&
&
&
&
&
&
&
24&
23&
&
&
20&
19&
&
&
16&
15&
&
&
12&
11&
&
&
8&
7&
&
&
&
&
&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x2c}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}&
\multicolumn{4}{c|}{C}&
\multicolumn{4}{c|}{opcode 0x6}&
\multicolumn{8}{c|}{reserved}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{8}{c|}{8 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.xor32\ rA,rB,rC}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large The contents of general register rB are combined with the contents of general register rC in a bit-wise logical XOR operation. The result is placed into general register rA.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
rA <- rB XOR rC
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.mul32s}&
\multicolumn{1}{c}{\textbf{\huge Multiply Signed}}&
\textbf{\huge l.mul32s}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccc|cccc|cccccccc|}
\hline
31&
&
&
&
&
&
&
24&
23&
&
&
20&
19&
&
&
16&
15&
&
&
12&
11&
&
&
8&
7&
&
&
&
&
&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x2c}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}&
\multicolumn{4}{c|}{C}&
\multicolumn{4}{c|}{opcode 0x7}&
\multicolumn{8}{c|}{reserved}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{8}{c|}{8 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.mul32s\ rA,rB,rC}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large The contents of general register rB and the contents of general register rC are multiplied and the result is truncated to 32 bits and placed into general register rA. Both operands are treated as unsigned integers.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
rA <- rB * rC
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 2: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Recommended\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.mul32u}&
\multicolumn{1}{c}{\textbf{\huge Multiply Unsigned}}&
\textbf{\huge l.mul32u}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccc|cccc|cccccccc|}
\hline
31&
&
&
&
&
&
&
24&
23&
&
&
20&
19&
&
&
16&
15&
&
&
12&
11&
&
&
8&
7&
&
&
&
&
&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x2c}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}&
\multicolumn{4}{c|}{C}&
\multicolumn{4}{c|}{opcode 0x8}&
\multicolumn{8}{c|}{reserved}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{8}{c|}{8 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.mul32u\ rA,rB,rC}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large The contents of general register rB and the contents of general register rC are multiplied and the result is truncated to 32 bits and placed into general register rA. Both operands are treated as unsigned integers.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
rA <- rB * rC
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 2: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Recommended\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.div32s}&
\multicolumn{1}{c}{\textbf{\huge Divide Signed}}&
\textbf{\huge l.div32s}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccc|cccc|cccccccc|}
\hline
31&
&
&
&
&
&
&
24&
23&
&
&
20&
19&
&
&
16&
15&
&
&
12&
11&
&
&
8&
7&
&
&
&
&
&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x2c}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}&
\multicolumn{4}{c|}{C}&
\multicolumn{4}{c|}{opcode 0x9}&
\multicolumn{8}{c|}{reserved}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{8}{c|}{8 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.div32s\ rA,rB,rC}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large The contents of general register rB are divided by the contents of general register rC and the result is placed into general register rA. Both operands are treated as signed integers. A divisor flag is set when the divisor is zero.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
rA <- rB / rC
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 3: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Optional\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.div32u}&
\multicolumn{1}{c}{\textbf{\huge Divide Unsigned}}&
\textbf{\huge l.div32u}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|cccc|cccc|cccc|cccccccc|}
\hline
31&
&
&
&
&
&
&
24&
23&
&
&
20&
19&
&
&
16&
15&
&
&
12&
11&
&
&
8&
7&
&
&
&
&
&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x2c}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}&
\multicolumn{4}{c|}{C}&
\multicolumn{4}{c|}{opcode 0xa}&
\multicolumn{8}{c|}{reserved}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{8}{c|}{8 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.div32u\ rA,rB,rC}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large The contents of general register rB are divided by the contents of general register rC and the result is placed into general register rA. Both operands are treated as unsigned integers. A divisor flag is set when the divisor is zero.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
rA <- rB / rC
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 3: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Optional\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.dcbf}&
\multicolumn{1}{c}{\textbf{\huge Data Cache Block Flush}}&
\textbf{\huge l.dcbf}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|cccccccc|cccc|cccccccc|}
\hline
31&
&
&
&
&
&
&
24&
23&
&
&
20&
19&
&
&
&
&
&
&
12&
11&
&
&
8&
7&
&
&
&
&
&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x30}&
\multicolumn{4}{c|}{A}&
\multicolumn{8}{c|}{J}&
\multicolumn{4}{c|}{opcode 0x0}&
\multicolumn{8}{c|}{J}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{8}{c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{8}{c|}{8 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.dcbf\ J(rA)}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large TBD}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 5: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Cache Management&Supervisor only&Mandatory if cache supported\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.dcbt}&
\multicolumn{1}{c}{\textbf{\huge Data Cache Block Touch}}&
\textbf{\huge l.dcbt}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|cccccccc|cccc|cccccccc|}
\hline
31&
&
&
&
&
&
&
24&
23&
&
&
20&
19&
&
&
&
&
&
&
12&
11&
&
&
8&
7&
&
&
&
&
&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x30}&
\multicolumn{4}{c|}{A}&
\multicolumn{8}{c|}{J}&
\multicolumn{4}{c|}{opcode 0x1}&
\multicolumn{8}{c|}{J}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{8}{c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{8}{c|}{8 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.dcbt\ J(rA)}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large TBD}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 5: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Cache Management&Supervisor only&Mandatory if cache supported\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.dcbi}&
\multicolumn{1}{c}{\textbf{\huge Data Cache Block Invalidate}}&
\textbf{\huge l.dcbi}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|cccccccc|cccc|cccccccc|}
\hline
31&
&
&
&
&
&
&
24&
23&
&
&
20&
19&
&
&
&
&
&
&
12&
11&
&
&
8&
7&
&
&
&
&
&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x30}&
\multicolumn{4}{c|}{A}&
\multicolumn{8}{c|}{J}&
\multicolumn{4}{c|}{opcode 0x2}&
\multicolumn{8}{c|}{J}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{8}{c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{8}{c|}{8 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.dcbi\ J(rA)}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large TBD}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 5: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Cache Management&Supervisor only&Mandatory if cache supported\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.dcia}&
\multicolumn{1}{c}{\textbf{\huge Data Cache Invalidate All}}&
\textbf{\huge l.dcia}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|cccccccc|cccc|cccccccc|}
\hline
31&
&
&
&
&
&
&
24&
23&
&
&
20&
19&
&
&
&
&
&
&
12&
11&
&
&
8&
7&
&
&
&
&
&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x30}&
\multicolumn{4}{c|}{A}&
\multicolumn{8}{c|}{reserved}&
\multicolumn{4}{c|}{opcode 0x3}&
\multicolumn{8}{c|}{reserved}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{8}{c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{8}{c|}{8 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.dcia\ }{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large TBD}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 5: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Cache Management&Supervisor only&Mandatory if cache supported\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.dcfa}&
\multicolumn{1}{c}{\textbf{\huge Data Cache Flush All}}&
\textbf{\huge l.dcfa}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|cccccccc|cccc|cccccccc|}
\hline
31&
&
&
&
&
&
&
24&
23&
&
&
20&
19&
&
&
&
&
&
&
12&
11&
&
&
8&
7&
&
&
&
&
&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x30}&
\multicolumn{4}{c|}{A}&
\multicolumn{8}{c|}{reserved}&
\multicolumn{4}{c|}{opcode 0x4}&
\multicolumn{8}{c|}{reserved}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{8}{c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{8}{c|}{8 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.dcfa\ }{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large TBD}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 5: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Cache Management&Supervisor only&Mandatory if cache supported\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.tlbia}&
\multicolumn{1}{c}{\textbf{\huge TLB Invalidate All}}&
\textbf{\huge l.tlbia}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|cccccccc|cccc|cccccccc|}
\hline
31&
&
&
&
&
&
&
24&
23&
&
&
20&
19&
&
&
&
&
&
&
12&
11&
&
&
8&
7&
&
&
&
&
&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x30}&
\multicolumn{4}{c|}{A}&
\multicolumn{8}{c|}{reserved}&
\multicolumn{4}{c|}{opcode 0x5}&
\multicolumn{8}{c|}{reserved}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{8}{c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{8}{c|}{8 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.tlbia\ }{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large TBD}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 6: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Virtual Memory&Supervisor only&Mandatory if MMU supported\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.mtsr}&
\multicolumn{1}{c}{\textbf{\huge Move To Special Register}}&
\textbf{\huge l.mtsr}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|cccccccc|cccc|cccccccc|}
\hline
31&
&
&
&
&
&
&
24&
23&
&
&
20&
19&
&
&
&
&
&
&
12&
11&
&
&
8&
7&
&
&
&
&
&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x30}&
\multicolumn{4}{c|}{A}&
\multicolumn{8}{c|}{S}&
\multicolumn{4}{c|}{opcode 0x6}&
\multicolumn{8}{c|}{S}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{8}{c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{8}{c|}{8 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.mtsr\ rS,rA}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large The contents of general register rA are moved into special register rS.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
rS <- rA
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 4: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
System Management&Supervisor only&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge l.mfsr}&
\multicolumn{1}{c}{\textbf{\huge Move From Special Register}}&
\textbf{\huge l.mfsr}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|cccccccc|cccc|cccccccc|}
\hline
31&
&
&
&
&
&
&
24&
23&
&
&
20&
19&
&
&
&
&
&
&
12&
11&
&
&
8&
7&
&
&
&
&
&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x30}&
\multicolumn{4}{c|}{A}&
\multicolumn{8}{c|}{S}&
\multicolumn{4}{c|}{opcode 0x7}&
\multicolumn{8}{c|}{S}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{8}{c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{8}{c|}{8 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large l.mfsr\ rA,rS}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large The contents of special register rS are moved into general register rA.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
rA <- rS
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 4: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
System Management&Supervisor only&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge h.sfeq32}&
\multicolumn{1}{c}{\textbf{\huge Set Flag if Equal}}&
\textbf{\huge h.sfeq32}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|cccc|}
\hline
15&
&
&
&
&
&
&
8&
7&
&
&
4&
3&
&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x40}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large h.sfeq32\ rA,rB}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large The contents of general register rA and the contents of general register rB are compared. If the two registers are equal, then the compare flag is set; otherwise the compare flag is cleared.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
flag <- rA == rB
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge h.sfne32}&
\multicolumn{1}{c}{\textbf{\huge Set Flag if Not Equal}}&
\textbf{\huge h.sfne32}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|cccc|}
\hline
15&
&
&
&
&
&
&
8&
7&
&
&
4&
3&
&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x41}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large h.sfne32\ rA,rB}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large The contents of general register rA and the contents of general register rB are compared. If the two registers are not equal, then the compare flag is set; otherwise the compare flag is cleared.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
flag <- rA != rB
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge h.sfgt32s}&
\multicolumn{1}{c}{\textbf{\huge Set Flag if Greater Than Signed}}&
\textbf{\huge h.sfgt32s}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|cccc|}
\hline
15&
&
&
&
&
&
&
8&
7&
&
&
4&
3&
&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x42}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large h.sfgt32s\ rA,rB}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large The contents of general register rA and the contents of general register rB are compared as signed integers. If the contents of the first register are greater than the contents of the second register, then the compare flag is set; otherwise the compare flag is cleared.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
flag <- rA > rB
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge h.sfge32s}&
\multicolumn{1}{c}{\textbf{\huge Set Flag if Greater or Equal Than Signed}}&
\textbf{\huge h.sfge32s}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|cccc|}
\hline
15&
&
&
&
&
&
&
8&
7&
&
&
4&
3&
&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x43}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large h.sfge32s\ rA,rB}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large The contents of general register rA and the contents of general register rB are compared as signed integers. If the contents of the first register are greater or equal than the contents of the second register, then the compare flag is set; otherwise the compare flag is cleared.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
flag <- rA >= rB
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge h.sflt32s}&
\multicolumn{1}{c}{\textbf{\huge Set Flag if Less Than Signed}}&
\textbf{\huge h.sflt32s}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|cccc|}
\hline
15&
&
&
&
&
&
&
8&
7&
&
&
4&
3&
&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x44}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large h.sflt32s\ rA,rB}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large The contents of general register rA and the contents of general register rB are compared as signed integers. If the contents of the first register are less than the contents of the second register, then the compare flag is set; otherwise the compare flag is cleared.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
flag <- rA < rB
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge h.sfle32s}&
\multicolumn{1}{c}{\textbf{\huge Set Flag if Less or Equal Than Signed}}&
\textbf{\huge h.sfle32s}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|cccc|}
\hline
15&
&
&
&
&
&
&
8&
7&
&
&
4&
3&
&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x45}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large h.sfle32s\ rA,rB}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large The contents of general register rA and the contents of general register rB are compared as signed integers. If the contents of the first register are less or equal than the contents of the second register, then the compare flag is set; otherwise the compare flag is cleared.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
flag <- rA <= rB
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge h.sfgt32u}&
\multicolumn{1}{c}{\textbf{\huge Set Flag if Greater Than Unsigned}}&
\textbf{\huge h.sfgt32u}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|cccc|}
\hline
15&
&
&
&
&
&
&
8&
7&
&
&
4&
3&
&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x46}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large h.sfgt32u\ rA,rB}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large The contents of general register rA and the contents of general register rB are compared as unsigned integers. If the contents of the first register are greater than the contents of the second register, then the compare flag is set; otherwise the compare flag is cleared.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
flag <- rA > rB
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge h.sfge32u}&
\multicolumn{1}{c}{\textbf{\huge Set Flag if Greater or Equal Than Unsigned}}&
\textbf{\huge h.sfge32u}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|cccc|}
\hline
15&
&
&
&
&
&
&
8&
7&
&
&
4&
3&
&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x47}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large h.sfge32u\ rA,rB}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large The contents of general register rA and the contents of general register rB are compared as unsigned integers. If the contents of the first register are greater or equal than the contents of the second register, then the compare flag is set; otherwise the compare flag is cleared.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
flag <- rA >= rB
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge h.sflt32u}&
\multicolumn{1}{c}{\textbf{\huge Set Flag if Less Than Unsigned}}&
\textbf{\huge h.sflt32u}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|cccc|}
\hline
15&
&
&
&
&
&
&
8&
7&
&
&
4&
3&
&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x48}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large h.sflt32u\ rA,rB}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large The contents of general register rA and the contents of general register rB are compared as unsigned integers. If the contents of the first register are less than the contents of the second register, then the compare flag is set; otherwise the compare flag is cleared.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
flag <- rA < rB
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge h.sfle32u}&
\multicolumn{1}{c}{\textbf{\huge Set Flag if Less or Equal Than Unsigned}}&
\textbf{\huge h.sfle32u}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|cccc|}
\hline
15&
&
&
&
&
&
&
8&
7&
&
&
4&
3&
&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x49}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large h.sfle32u\ rA,rB}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large The contents of general register rA and the contents of general register rB are compared as unsigned integers. If the contents of the first register are less or equal than the contents of the second register, then the compare flag is set; otherwise the compare flag is cleared.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
flag <- rA <= rB
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge h.mov32}&
\multicolumn{1}{c}{\textbf{\huge Move}}&
\textbf{\huge h.mov32}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|cccc|}
\hline
15&
&
&
&
&
&
&
8&
7&
&
&
4&
3&
&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x4a}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large h.mov32\ rA,rB}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large The contents of general register rB are moved into general register rA.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
rA <- rB
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 2: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Recommended\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge h.ext16s}&
\multicolumn{1}{c}{\textbf{\huge Extend Half Word with Sign}}&
\textbf{\huge h.ext16s}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|c|ccc|}
\hline
15&
&
&
&
&
&
&
8&
7&
&
&
4&
3&
2&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x4b}&
\multicolumn{4}{c|}{A}&
\multicolumn{1}{c|}{reserved}&
\multicolumn{3}{c|}{opcode 0x0}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{1}{c|}{1 bits}&
\multicolumn{3}{c|}{3 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large h.ext16s\ rA}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large Bit 15 of general register rA is placed in high-order 16 bits of general register rA. The low-order 16 bits of general register rA are left unchanged.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
rA{[}31:16{]} <- rA{[}15{]}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 2: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Recommended\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge h.ext16z}&
\multicolumn{1}{c}{\textbf{\huge Extend Half Word with Zero}}&
\textbf{\huge h.ext16z}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|c|ccc|}
\hline
15&
&
&
&
&
&
&
8&
7&
&
&
4&
3&
2&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x4b}&
\multicolumn{4}{c|}{A}&
\multicolumn{1}{c|}{reserved}&
\multicolumn{3}{c|}{opcode 0x1}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{1}{c|}{1 bits}&
\multicolumn{3}{c|}{3 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large h.ext16z\ rA}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large Zero is placed in high-order 16 bits of general register rA. The low-order 16 bits of general register rA are left unchanged.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
rA{[}31:16{]} <- 0
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 2: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Recommended\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge h.ext8s}&
\multicolumn{1}{c}{\textbf{\huge Extend Byte with Sign}}&
\textbf{\huge h.ext8s}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|c|ccc|}
\hline
15&
&
&
&
&
&
&
8&
7&
&
&
4&
3&
2&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x4b}&
\multicolumn{4}{c|}{A}&
\multicolumn{1}{c|}{reserved}&
\multicolumn{3}{c|}{opcode 0x2}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{1}{c|}{1 bits}&
\multicolumn{3}{c|}{3 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large h.ext8s\ rA}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large Bit 7 of general register rA is placed in high-order 24 bits of general register rA. The low-order eight bits of general register rA are left unchanged.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
rA{[}31:8{]} <- rA{[}7{]}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 2: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Recommended\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge h.ext8z}&
\multicolumn{1}{c}{\textbf{\huge Extend Byte with Zero}}&
\textbf{\huge h.ext8z}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|c|ccc|}
\hline
15&
&
&
&
&
&
&
8&
7&
&
&
4&
3&
2&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x4b}&
\multicolumn{4}{c|}{A}&
\multicolumn{1}{c|}{reserved}&
\multicolumn{3}{c|}{opcode 0x3}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{1}{c|}{1 bits}&
\multicolumn{3}{c|}{3 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large h.ext8z\ rA}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large Zero is placed in high-order 24 bits of general register rA. The low-order eight bits of general register rA are left unchanged.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
rA{[}31:8{]} <- 0
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 2: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Recommended\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge h.nop}&
\multicolumn{1}{c}{\textbf{\huge No Operation}}&
\textbf{\huge h.nop}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|ccccc|ccc|}
\hline
15&
&
&
&
&
&
&
8&
7&
&
&
&
3&
2&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x4b}&
\multicolumn{5}{c|}{reserved}&
\multicolumn{3}{c|}{opcode 0x4}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{5}{c|}{5 bits}&
\multicolumn{3}{c|}{3 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large h.nop\ }{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large This instruction does not do anything except it takes at least one clock cycle to complete. It is usually used to fill gaps between 16 bit and 32 bit instructions.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge h.jalr}&
\multicolumn{1}{c}{\textbf{\huge Jump and Link Register}}&
\textbf{\huge h.jalr}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccccccc|cccc|c|ccc|}
\hline
15&
&
&
&
&
&
&
8&
7&
&
&
4&
3&
2&
&
0\\
\hline
\multicolumn{8}{|c|}{opcode 0x4b}&
\multicolumn{4}{c|}{A}&
\multicolumn{1}{c|}{reserved}&
\multicolumn{3}{c|}{opcode 0x5}\\
 
\hline
\multicolumn{8}{|c|}{8 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{1}{c|}{1 bits}&
\multicolumn{3}{c|}{3 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large h.jalr\ rA}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large The contents of general register rA is effective address of the jump. The program unconditionally jumps to EA with a delay of one 32 bit or two 16 bit instructions. The address of the instruction after the delay slot is placed in the link register. }{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
PC <- rA\\LR <- DelayInsnAddr + 4
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge h.load32u}&
\multicolumn{1}{c}{\textbf{\huge Load Word and Extend with Zero}}&
\textbf{\huge h.load32u}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccc|cccc|cccc|cccc|}
\hline
15&
&
&
12&
11&
&
&
8&
7&
&
&
4&
3&
&
&
0\\
\hline
\multicolumn{4}{|c|}{opcode 0x5}&
\multicolumn{4}{c|}{N}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}\\
 
\hline
\multicolumn{4}{|c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large h.load32u\ rA,N(rB)}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large Offset is sign-extended and added to the contents of general register rB. Sum represents effective address. The word in memory addressed by EA is loaded into general register rA. }{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
EA <- exts(Immediate) + rB\\rA <- (EA){[}31:0{]}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 2: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Recommended\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge h.stor32}&
\multicolumn{1}{c}{\textbf{\huge Store Word}}&
\textbf{\huge h.stor32}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccc|cccc|cccc|cccc|}
\hline
15&
&
&
12&
11&
&
&
8&
7&
&
&
4&
3&
&
&
0\\
\hline
\multicolumn{4}{|c|}{opcode 0x6}&
\multicolumn{4}{c|}{N}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}\\
 
\hline
\multicolumn{4}{|c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large h.stor32\ N(rA),rB}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large Offset is sign-extended and added to the contents of general register rA. Sum represents effective address. The word in general register rB is stored to memory addressed by EA. }{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
EA <- exts(Immediate) + rA\\(EA){[}31:0{]} <- rB
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 2: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Recommended\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge h.add32s}&
\multicolumn{1}{c}{\textbf{\huge Add Signed}}&
\textbf{\huge h.add32s}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccc|cccc|cccc|cccc|}
\hline
15&
&
&
12&
11&
&
&
8&
7&
&
&
4&
3&
&
&
0\\
\hline
\multicolumn{4}{|c|}{opcode 0x7}&
\multicolumn{4}{c|}{D}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{B}\\
 
\hline
\multicolumn{4}{|c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large h.add32s\ rA,rB,rD}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large The contents of general register rC is added to the contents of general register rB to form the result. The result is placed into general register rA.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
rA <- rB + rC
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 1: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Mandatory always\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge h.immch32s}&
\multicolumn{1}{c}{\textbf{\huge Immediate Byte Signed}}&
\textbf{\huge h.immch32s}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccc|cccc|cccc|cccc|}
\hline
15&
&
&
12&
11&
&
&
8&
7&
&
&
4&
3&
&
&
0\\
\hline
\multicolumn{4}{|c|}{opcode 0x8}&
\multicolumn{4}{c|}{M}&
\multicolumn{4}{c|}{A}&
\multicolumn{4}{c|}{M}\\
 
\hline
\multicolumn{4}{|c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}&
\multicolumn{4}{c|}{4 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large h.immch32s\ rA,M}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large 8 bit immediate is sign-extended to 32 bits and placed into general register rA.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
rA <- exts(Immediate)
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 2: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Recommended\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge h.jal}&
\multicolumn{1}{c}{\textbf{\huge Jump and Link}}&
\textbf{\huge h.jal}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccc|cccccccccccc|}
\hline
15&
&
&
12&
11&
&
&
&
&
&
&
&
&
&
&
0\\
\hline
\multicolumn{4}{|c|}{opcode 0x9}&
\multicolumn{12}{c|}{X}\\
 
\hline
\multicolumn{4}{|c|}{4 bits}&
\multicolumn{12}{c|}{12 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large h.jal\ X}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large The immediate is shifted left two bits, sign-extended to 32 bits and then added to the address of the delay slot. The result is effective address of the jump. The program unconditionally jumps to EA with a delay of one 32 bit or two 16 bit instructions. The address of the instruction after the delay slot is placed in the link register. }{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
PC <- (Immediate || 00) + DelayInsnAddr\\LR <- DelayInsnAddr + 4
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 2: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Recommended\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge h.jal}&
\multicolumn{1}{c}{\textbf{\huge Jump and Link}}&
\textbf{\huge h.jal}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccc|cccccccccccc|}
\hline
15&
&
&
12&
11&
&
&
&
&
&
&
&
&
&
&
0\\
\hline
\multicolumn{4}{|c|}{opcode 0xa}&
\multicolumn{12}{c|}{X}\\
 
\hline
\multicolumn{4}{|c|}{4 bits}&
\multicolumn{12}{c|}{12 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large h.jal\ X}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large The immediate is shifted left two bits, sign-extended to 32 bits and then added to the address of the delay slot. The result is effective address of the jump. The program unconditionally jumps to EA with a delay of one 32 bit or two 16 bit instructions. The address of the instruction after the delay slot is placed in the link register. }{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
PC <- (Immediate || 00) + DelayInsnAddr\\LR <- DelayInsnAddr + 4
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 2: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Recommended\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge h.bnf}&
\multicolumn{1}{c}{\textbf{\huge Branch if No Flag}}&
\textbf{\huge h.bnf}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccc|cccccccccccc|}
\hline
15&
&
&
12&
11&
&
&
&
&
&
&
&
&
&
&
0\\
\hline
\multicolumn{4}{|c|}{opcode 0xb}&
\multicolumn{12}{c|}{X}\\
 
\hline
\multicolumn{4}{|c|}{4 bits}&
\multicolumn{12}{c|}{12 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large h.bnf\ X}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large The immediate is shifted left two bits, sign-extended to 32 bits and then added to the address of the delay slot. The result is effective address of the branch. If the compare flag is cleared, then the program branches to EA with a delay of one 32 bit or two 16 bit instructions.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
EA <- (Immediate || 00) + DelayInsnAddr\\PC <- EA if flag cleared
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 2: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Recommended\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge h.bf}&
\multicolumn{1}{c}{\textbf{\huge Branch if Flag}}&
\textbf{\huge h.bf}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccc|cccccccccccc|}
\hline
15&
&
&
12&
11&
&
&
&
&
&
&
&
&
&
&
0\\
\hline
\multicolumn{4}{|c|}{opcode 0xc}&
\multicolumn{12}{c|}{X}\\
 
\hline
\multicolumn{4}{|c|}{4 bits}&
\multicolumn{12}{c|}{12 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large h.bf\ X}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large The immediate is shifted left two bits, sign-extended to 32 bits and then added to the address of the delay slot. The result is effective address of the branch. If the compare flag is set, then the program branches to EA with a delay of one 32 bit or two 16 bit instructions.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
EA <- (Immediate || 00) + DelayInsnAddr\\PC <- EA if flag set
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 2: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Recommended\\
\hline
\end{tabular}\par}
 
 
 
\newpage
\vspace{10mm}
\lyxline{\small}\vspace{-1\parskip}
\vspace{10mm}
{\raggedright \begin{tabular}{ccc}
\textbf{\textcolor{white}{\small Left}}\textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Middle Middle
Middle Middle Middle Middle Middle Middle}} \textcolor{white}{\small }&
\textcolor{white}{\small }\textbf{\textcolor{white}{\small Right}}\\
\textbf{\huge h.sched}&
\multicolumn{1}{c}{\textbf{\huge Schedule}}&
\textbf{\huge h.sched}\\
\end{tabular}\par}
\bigskip{}
 
\vspace{10mm}
{\centering \begin{tabular}{|cccc|cccccccccccc|}
\hline
15&
&
&
12&
11&
&
&
&
&
&
&
&
&
&
&
0\\
\hline
\multicolumn{4}{|c|}{opcode 0xf}&
\multicolumn{12}{c|}{Z}\\
 
\hline
\multicolumn{4}{|c|}{4 bits}&
\multicolumn{12}{c|}{12 bits}\\
 
\hline
\end{tabular}\par}
\vspace{15mm}
{\par\raggedright \textbf{\LARGE Format:}\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large h.sched\ Z}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Description:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
\texttt{\large Immediate carries static scheduling information about instruction scheduling. This information is generated by an optimizing compiler.}{\large \par}
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Operation:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\textbf{\LARGE Notes:}{\LARGE \par}
\vspace{5mm}
\begin{quotation}
 
\end{quotation}
\vspace{10mm}
\vfill
Class 3: 
{\centering \begin{tabular}{|c|c|c|}
\hline
Architecture Level&
Execution Mode&
Implementation\\
\hline
Core CPU&User and Supervisor&Optional\\
\hline
\end{tabular}\par}
 
 
\end{document}