Subversion Repositories or1k

/* Information about OR1K ISA. W/o this we can't generate or1k_isa_part.tex.
*/
 
struct or1k_isa {
	char *name;
	char *title;
	char *desc;
	char *oper32;
	char *oper64;
	char *except;
	int  class;
	int  printed;
};
 
#define ORBIS32I	1
#define ORBIS32II	2
#define ORBIS64I	3
#define ORBIS64II	4
#define ORFPX32I	5
#define ORFPX32II	6
#define ORFPX64I	7
#define ORFPX64II	8
#define ORVDX64I	9
#define ORVDX64II	10
 
static struct or1k_isa or1k_isa_info[] =
{
 
/*** ORBIS32 ***/
 
{"l.addi", "Add Immediate Signed",
	"Immediate is signed-extended and added to the contents of general-purpose"
	"register rA to form the result. The result is placed into general-purpose"
	"register rD.",
	"rD[31:0] <- rA[31:0] + exts(Immediate)\\SR[CY] <- carry\\SR[OV] <- overflow",
	"rD[63:0] <- rA[63:0] + exts(Immediate)\\SR[CY] <- carry\\SR[OV] <- overflow",
	"Range Exception", ORBIS32I,},
 
{"l.andi", "And with Immediate Half Word",
	"Immediate is zero-extended and combined with the contents "
	"of general-purpose register rB in a bit-wise logical AND operation. The "
	"result is placed into general-purpose register rD.",
	"rD[31:0] <- rB[31:0] AND extz(Immediate)",
	"rD[63:0] <- rB[63:0] AND extz(Immediate)",
	"None", ORBIS32I,},
 
{"l.ori", "Or with Immediate Half Word",
	"Immediate is zero-extended and combined with the contents "
	"of general-purpose register rB in a bit-wise logical OR operation. The "
	"result is placed into general-purpose register rD.",
	"rD[31:0] <- rB[31:0] OR extz(Immediate)",
	"rD[63:0] <- rB[63:0] OR extz(Immediate)",
	"None", ORBIS32I,},
 
{"l.xori", "Exclusive Or with Immediate Half Word",
	"Immediate is zero-extended and combined with the contents of general-purpose "
	"register rB in a bit-wise logical XOR operation. The result is "
	"placed into general-purpose register rD.",
	"rD[31:0] <- rB[31:0] XOR exts(Immediate)",
	"rD[63:0] <- rB[63:0] XOR exts(Immediate)",
	"None", ORBIS32I,},
 
{"l.slli", "Shift Left Logical with Immediate",
	"6-bit immediate specifies the number of "
	"bit positions the contents of general-purpose register rA are shifted left, "
	"inserting zeros into the low-order bits. Result is written into general-purpose "
	"rD.",
	"rD[31:L] <- rA[31-L:0]\\rD[L-1:0] <- 0",
	"rD[63:L] <- rA[63-L:0]\\rD[L-1:0] <- 0",
	"None", ORBIS32I,},
 
{"l.srai", "Shift Right Arithmetic with Immediate",
	"6-bit immediate specifies the number of "
	"bit positions the contents of general-purpose register rA are shifted right, "
	"sign-extending the high-order bits. Result is written into "
	"general-purpose register rD.",
	"rD[31-L:0] <- rA[31:L]\\rD[31:32-L] <- rA[31]",
	"rD[63-L:0] <- rA[63:L]\\rD[63:64-L] <- rA[63]",
	"None", ORBIS32I,},
 
{"l.srli", "Shift Right Logical with Immediate",
	"6-bit Immediate specifies the number of "
	"bit positions the contents of general-purpose register rA are shifted right, "
	"inserting zeros into the high-order bits. Result is written into general-purpose "
	"register rD.",
	"rD[31-L:0] <- rA[31:L]\\rD[31:32-L] <- 0",
	"rD[63-L:0] <- rA[63:L]\\rD[63:64-L] <- 0",
	"None", ORBIS32I,},
 
{"l.rori", "Rotate Right with Immediate",
	"6-bit immediate specifies the number of "
	"bit positions the contents of general-purpose register rA are rotated right. "
	"Result is written into general-purpose register rD.",
	"rD[31-L:0] <- rA[31:L]\\rD[31:32-L] <- rA[L-1:0]",
	"rD[63-L:0] <- rA[63:L]\\rD[63:64-L] <- rA[L-1:0]",
	"None", ORBIS32I,},
 
{"l.muli", "Multiply Immediate Signed",
	"Immediate and the contents of general-purpose register rA are "
	"multiplied and the result is truncated to destination register width and placed into "
	"general-purpose register rD.",
	"rD[31:0] <- rA[31:0] * Immediate\\SR[OV] <- overflow",
	"rD[63:0] <- rA[63:0] * Immediate\\SR[OV] <- overflow",
	"None", ORBIS32I,},
 
{"l.maci", "Multiply Immediate Signed and Accumulate",
	"Immediate and the contents of general-purpose register rA are "
	"multiplied and the result is truncated to 32 bits and added "
	"to the special-purpose registers MACHI and MACLO. "
	"All operands are treated as signed integers.",
	"M[31:0] <- rA[31:0] * Immediate\\MACHI[31:0]MACLO[31:0] <- M[31:0] + MACHI[31:0]MACLO[31:0]\\"
	"SR[OV] <- overflow",
	"M[31:0] <- rA[63:0] * Immediate\\MACHI[31:0]MACLO[31:0] <- M[31:0] + MACHI[31:0]MACLO[31:0]\\"
	"SR[OV] <- overflow",
	"None", ORBIS32II,},
 
{"l.exths", "Extend Half Word with Sign",
	"Bit 15 of general-purpose register rA is placed in high-order bits of "
	"general-purpose register rD. The low-order 16 bits of general-purpose register rA "
	"are copied into low-order 16 bits of general-purpose register rD.",
	"rD[31:16] <- rA[15]\\rD[15:0] <- rA[15:0]",
	"rD[63:16] <- rA[15]\\rD[15:0] <- rA[15:0]",
	"None", ORBIS32II,},
 
{"l.extbs", "Extend Byte with Sign",
	"Bit 7 of general-purpose register rA is placed in high-order bits of "
	"general-purpose register rD. The low-order eight bits of general-purpose register rA "
	"are copied from low-order eight bits of general-purpose register rD.",
	"rD[31:8] <- rA[7]\\rD[7:0] <- rA[7:0]",
	"rD[63:8] <- rA[7]\\rD[7:0] <- rA[7:0]",
	"None", ORBIS32II,},
 
{"l.extbz", "Extend Byte with Zero",
	"Zero is placed in high-order bits of "
	"general-purpose register rD. The low-order eight bits of general-purpose register rA "
	"are copied into low-order eight bits of general-purpose register rD.",
	"rD[31:8] <- 0\\rD[7:0] <- rA[7:0]",
	"rD[63:8] <- 0\\rD[7:0] <- rA[7:0]",
	"None", ORBIS32II,},
 
{"l.exthz", "Extend Half Word with Zero",
	"Zero is placed in high-order bits of "
	"general-purpose register rD. The low-order 16 bits of general-purpose register rA "
	"are copied into low-order 16 bits of general-purpose register rD.",
	"rD[31:16] <- 0\\rD[15:0] <- rA[15:0]",
	"rD[63:16] <- 0\\rD[15:0] <- rA[15:0]",
	"None", ORBIS32II,},
 
{"l.extwz", "Extend Word with Zero",
	"Zero is placed in high-order bits of "
	"general-purpose register rD. The low-order 32 bits of general-purpose register rA "
	"are copied into low-order 32 bits of general-purpose register rD.",
	"rD[31:0] <- rA[31:0]",
	"rD[63:32] <- 0\\rD[31:0] <- rA[31:0]",
	"None", ORBIS64II,},
 
{"l.extws", "Extend Word with Sign",
	"Bit 31 of general-purpose register rA is placed in high-order bits of "
	"general-purpose register rD. The low-order 32 bits of general-purpose register rA "
	"are copied from low-order 32 bits of general-purpose register rD.",
	"rD[31:0] <- rA[31:0]",
	"rD[63:32] <- rA[31]\\rD[31:0] <- rA[31:0]",
	"None", ORBIS64II,},
 
{"l.cmov", "Conditional Move",
	"If SR[CF] is set, general-purpose register rA is placed in "
	"general-purpose register rD. If SR[CF] is cleared, general-purpose register rB "
	"is placed in general-purpose register rD.",
	"rD[31:0] <- SR[CF] ? rA[31:0] : rB[31:0]",
	"rD[63:0] <- SR[CF] ? rA[63:0] : rB[63:0]",
	"None", ORBIS32II,},
 
{"l.ff1", "Find First 1",
	"Position of the first '1' bit is written into general-purpose register rD. Checking for "
	"bit '1' starts with MSB and counting is decremented for every zero bit. If first '1' bit is "
	"discovered in LSB, one is written into rD. If there is no '1' bits, zero is written in rD.",
	"rD[31:0] <- rA[31] ? 32 : rA[30] ? 31 ... r[0] ? 1 : 0",
	"rD[63:0] <- rA[63] ? 64 : rA[62] ? 63 ... r[0] ? 1 : 0",
	"None", ORBIS32II,},
 
{"l.lbs", "Load Byte and Extend with Sign",
	"Offset is sign-extended and added to the contents of general-purpose "
	"register rA. Sum represents effective address. The byte in memory "
	"addressed by EA is loaded into the low-order eight bits of "
	"general-purpose register rD. "
	"High-order bits of general-purpose register rD are replaced with "
	"bit 7 of the loaded value.",
	"EA <- exts(Immediate) + rA[31:0]\\rD[7:0] <- (EA)[7:0]\\rD[31:8] <- rA[8]",
	"EA <- exts(Immediate) + rA[63:0]\\rD[7:0] <- (EA)[7:0]\\rD[63:8] <- rA[8]",
	"TLB miss\\Page fault\\Bus error", ORBIS32I,},
 
{"l.lhs", "Load Half Word and Extend with Sign",
	"Offset is sign-extended and added to the contents of general-purpose "
	"register rA. Sum represents effective address. The half word in memory "
	"addressed by EA is loaded into the low-order 16 bits of "
	"general-purpose register rD. "
	"High-order bits of general-purpose register rD are replaced with "
	"bit 15 of the loaded value.",
	"EA <- exts(Immediate) + rA[31:0]\\rD[15:0] <- (EA)[15:0]\\rD[31:16] <- rA[15]",
	"EA <- exts(Immediate) + rA[63:0]\\rD[15:0] <- (EA)[15:0]\\rD[63:16] <- rA[15]",
	"TLB miss\\Page fault\\Bus error", ORBIS32I,},
 
{"l.lws", "Load Single Word and Extend with Sign",
	"Offset is sign-extended and added to the contents of general-purpose "
	"register rA. Sum represents effective address. The single word in memory "
	"addressed by EA is loaded into the low-order 32 bits of "
	"general-purpose register rD. "
	"High-order bits of general-purpose register rD are replaced with "
	"bit 31 of the loaded value.",
	"EA <- exts(Immediate) + rA[31:0]\\rD[31:0] <- (EA)[31:0]",
	"EA <- exts(Immediate) + rA[63:0]\\rD[31:0] <- (EA)[31:0]\\rD[63:32] <- rA[31]",
	"TLB miss\\Page fault\\Bus error", ORBIS32I,},
 
{"l.lbz", "Load Byte and Extend with Zero",
	"Offset is sign-extended and added to the contents of general-purpose "
	"register rA. Sum represents effective address. The byte in memory "
	"addressed by EA is loaded into the low-order eight bits of "
	"general-purpose register rD. "
	"High-order bits of general-purpose register rD are replaced with "
	"zero.",
	"EA <- exts(Immediate) + rA[31:0]\\rD[7:0] <- (EA)[7:0]\\rD[31:8] <- 0",
	"EA <- exts(Immediate) + rA[63:0]\\rD[7:0] <- (EA)[7:0]\\rD[63:8] <- 0",
	"TLB miss\\Page fault\\Bus error", ORBIS32I,},
 
{"l.lhz", "Load Half Word and Extend with Zero",
	"Offset is sign-extended and added to the contents of general-purpose "
	"register rA. Sum represents effective address. The half word in memory "
	"addressed by EA is loaded into the low-order 16 bits of "
	"general-purpose register rD. "
	"High-order bits of general-purpose register rD are replaced with "
	"zero.",
	"EA <- exts(Immediate) + rA[31:0]\\rD[15:0] <- (EA)[15:0]\\rD[31:16] <- 0",
	"EA <- exts(Immediate) + rA[63:0]\\rD[15:0] <- (EA)[15:0]\\rD[63:16] <- 0",
	"TLB miss\\Page fault\\Bus error", ORBIS32I,},
 
{"l.lwz", "Load Single Word and Extend with Zero",
	"Offset is sign-extended and added to the contents of general-purpose "
	"register rA. Sum represents effective address. The single word in memory "
	"addressed by EA is loaded into the low-order 32 bits of "
	"general-purpose register rD. "
	"High-order bits of general-purpose register rD are replaced with "
	"zero.",
	"EA <- exts(Immediate) + rA[31:0]\\rD[31:0] <- (EA)[31:0]",
	"EA <- exts(Immediate) + rA[63:0]\\rD[31:0] <- (EA)[31:0]\\rD[63:32] <- 0",
	"TLB miss\\Page fault\\Bus error", ORBIS32I,},
 
{"l.ld", "Load Double Word",
	"Offset is sign-extended and added to the contents of general-purpose "
	"register rA. Sum represents effective address. The double word in memory "
	"addressed by EA is loaded into general-purpose register rD. ",
	"N/A",
	"EA <- exts(Immediate) + rA[63:0]\\rD[63:0] <- (EA)[63:0]",
	"TLB miss\\Page fault\\Bus error", ORBIS64I,},
 
{"l.sd", "Store Double Word",
	"Offset is sign-extended and added to the contents of general-purpose "
	"register rA. Sum represents effective address. The double word in "
	"general-purpose register rB is stored to memory location addressed by EA. ",
	"N/A",
	"EA <- exts(Immediate) + rA[63:0]\\(EA)[63:0] <- rB[63:0]",
	"TLB miss\\Page fault\\Bus error", ORBIS64I,},
 
{"l.sw", "Store Single Word",
	"Offset is sign-extended and added to the contents of general-purpose "
	"register rA. Sum represents effective address. The low-order 32 bits of "
	"general-purpose register rB are stored to memory location addressed by EA. ",
	"EA <- exts(Immediate) + rA[31:0]\\(EA)[31:0] <- rB[31:0]",
	"EA <- exts(Immediate) + rA[63:0]\\(EA)[31:0] <- rB[31:0]",
	"TLB miss\\Page fault\\Bus error", ORBIS32I,},
 
{"l.sh", "Store Half Word",
	"Offset is sign-extended and added to the contents of general-purpose "
	"register rA. Sum represents effective address. The low-order 16 bits "
	"of general-purpose register rB are stored to memory location addressed by EA. ",
	"EA <- exts(Immediate) + rA[31:0]\\(EA)[15:0] <- rB[15:0]",
	"EA <- exts(Immediate) + rA[63:0]\\(EA)[15:0] <- rB[15:0]",
	"TLB miss\\Page fault\\Bus error", ORBIS32I,},
 
{"l.sb", "Store Byte",
	"Offset is sign-extended and added to the contents of general-purpose "
	"register rA. Sum represents effective address. The low-order 8 bits "
	"of general-purpose register rB are stored to memory location addressed by EA. ",
	"EA <- exts(Immediate) + rA[31:0]\\(EA)[7:0] <- rB[7:0]",
	"EA <- exts(Immediate) + rA[63:0]\\(EA)[7:0] <- rB[7:0]",
	"TLB miss\\Page fault\\Bus error", ORBIS32I,},
 
{"l.add", "Add Signed",
	"The contents of general-purpose register rA is added to the contents "
	"of general-purpose register rB to form the result. The result is placed into "
	"general-purpose register rD.",
	"rD[31:0] <- rA[31:0] + rB[31:0]\\SR[CY] <- carry\\SR[OV] <- overflow",
	"rD[63:0] <- rA[63:0] + rB[63:0]\\SR[CY] <- carry\\SR[OV] <- overflow",
	"Range Exception", ORBIS32I,},
 
{"l.addc", "Add Signed and Carry",
	"The contents of general-purpose register rA is added to the contents "
	"of general-purpose register rB and carry SR[CY] to form the result. "
	"The result is placed into general-purpose register rD.",
	"rD[31:0] <- rA[31:0] + rB[31:0]\\SR[CY] <- carry\\SR[OV] <- overflow",
	"rD[63:0] <- rA[63:0] + rB[63:0]\\SR[CY] <- carry\\SR[OV] <- overflow",
	"Range Exception", ORBIS32I,},
 
{"l.sub", "Subtract Signed",
	"The contents of general-purpose register rB is subtracted from the contents "
	"of general-purpose register rA to form the result. The result is placed into "
	"general-purpose register rD.",
	"rD[31:0] <- rA[31:0] - rB[31:0]\\SR[CY] <- carry\\SR[OV] <- overflow",
	"rD[63:0] <- rA[63:0] - rB[63:0]\\SR[CY] <- carry\\SR[OV] <- overflow",
	"Range Exception", ORBIS32I,},
 
{"l.sll", "Shift Left Logical",
	"General-purpose register rB specifies the number of "
	"bit positions the contents of general-purpose register rA are shifted left, "
	"inserting zeros into the low-order bits. Result is written into general-purpose "
	"rD.",
	"rD[31:rB] <- rA[31-rB:0]\\rD[rB-1:0] <- 0",
	"rD[63:rB] <- rA[63-rB:0]\\rD[rB-1:0] <- 0",
	"None", ORBIS32I,},
 
{"l.sra", "Shift Right Arithmetic",
	"General-purpose register rB specifies the number of "
	"bit positions the contents of general-purpose register rA are shifted right, "
	"sign-extending the high-order bits. Result is written into "
	"general-purpose register rD.",
	"rD[31-rB:0] <- rA[31:rB]\\rD[31:32-rB] <- rB[31]",
	"rD[63-rB:0] <- rA[63:rB]\\rD[63:64-rB] <- rB[63]",
	"None", ORBIS32I,},
 
{"l.srl", "Shift Right Logical",
	"General-purpose register rB specifies the number of "
	"bit positions the contents of general-purpose register rA are shifted right, "
	"inserting zeros into the high-order bits. Result is written into general-purpose "
	"register rD.",
	"rD[31-rB:0] <- rA[31:rB]\\rD[31:32-rB] <- 0",
	"rD[63-rB:0] <- rA[63:rB]\\rD[63:64-rB] <- 0",
	"None", ORBIS32I,},
 
{"l.ror", "Rotate Right",
	"General-purpose register rB specifies the number of "
	"bit positions the contents of general-purpose register rA are rotated right. "
	"Result is written into general-purpose register rD.",
	"rD[31-rB:0] <- rA[31:rB]\\rD[31:32-rB] <- rA[rB-1:0]",
	"rD[63-rB:0] <- rA[63:rB]\\rD[63:64-rB] <- rA[rB-1:0]",
	"None", ORBIS32II,},
 
{"l.and", "And",
	"The contents of general-purpose register rA are combined with the contents "
	"of general-purpose register rB in a bit-wise logical AND operation. The "
	"result is placed into general-purpose register rD.",
	"rD[31:0] <- rA[31:0] AND rB[31:0]",
	"rD[63:0] <- rA[63:0] AND rB[63:0]",
	"None", ORBIS32I,},
 
{"l.or", "Or",
	"The contents of general-purpose register rA are combined with the contents "
	"of general-purpose register rB in a bit-wise logical OR operation. The "
	"result is placed into general-purpose register rD.",
	"rD[31:0] <- rA[31:0] OR rB[31:0]",
	"rD[63:0] <- rA[63:0] OR rB[63:0]",
	"None", ORBIS32I,},
 
{"l.xor", "Exclusive Or",
	"The contents of general-purpose register rA are combined with the contents "
	"of general-purpose register rB in a bit-wise logical XOR operation. The "
	"result is placed into general-purpose register rD.",
	"rD[31:0] <- rA[31:0] XOR rB[31:0]",
	"rD[63:0] <- rA[63:0] XOR rB[63:0]",
	"None", ORBIS32I,},
 
{"l.mac", "Multiply Signed and Accumulate",
	"The contents of general-purpose register rA and the contents of general-purpose "
	"register rB are multiplied and the result is truncated to 32 bits and added "
	"to the special-purpose registers MACHI and MACLO. "
	"All operands are treated as signed integers.",
	"M[31:0] <- rA[31:0] * rB[31:0]\\MACHI[31:0]MACLO[31:0] <- M[31:0] + MACHI[31:0]MACLO[31:0]\\"
	"SR[OV] <- overflow",
	"M[31:0] <- rA[63:0] * rB[63:0]\\MACHI[31:0]MACLO[31:0] <- M[31:0] + MACHI[31:0]MACLO[31:0]\\"
	"SR[OV] <- overflow",
	"None", ORBIS32II,},
 
{"l.mul", "Multiply Signed",
	"The contents of general-purpose register rA and the contents of general-purpose "
	"register rB are multiplied and the result is truncated to destination register width "
	"and placed into general-purpose register rD. "
	"Both operands are treated as unsigned integers.",
	"rD[31:0] <- rA[31:0] * rB[31:0]\\SR[OV] <- overflow",
	"rD[63:0] <- rA[63:0] * rB[63:0]\\SR[OV] <- overflow",
	"None", ORBIS32I,},
 
{"l.mulu", "Multiply Unsigned",
	"The contents of general-purpose register rA and the contents of general-purpose "
	"register rB are multiplied and the result is truncated to destination register width "
	"and placed into general-purpose register rD. "
	"Both operands are treated as unsigned integers.",
	"rD[31:0] <- rA[31:0] * rB[31:0]\\SR[OV] <- overflow",
	"rD[63:0] <- rA[63:0] * rB[63:0]\\SR[OV] <- overflow",
	"None", ORBIS32I,},
 
{"l.div", "Divide Signed",
	"The contents of general-purpose register rA are divided by the contents of "
	"general-purpose register rB and the result is placed into general-purpose register "
	"rD. Both operands are treated as signed integers. A divide by zero "
	"flag is set when the divisor is zero.",
	"rD[31:0] <- rA[31:0] / rB[31:0]\\SR[OV] <- overflow",
	"rD[63:0] <- rA[63:0] / rB[63:0]\\SR[OV] <- overflow",
	"None", ORBIS32II,},
 
{"l.divu", "Divide Unsigned",
	"The contents of general-purpose register rA are divided by the contents of "
	"general-purpose register rA and the result is placed into general-purpose register "
	"rD. Both operands are treated as unsigned integers. A divide by zero "
	"flag is set when the divisor is zero.",
	"rD[31:0] <- rA[31:0] / rB[31:0]\\SR[OV] <- overflow",
	"rD[63:0] <- rA[63:0] / rB[63:0]\\SR[OV] <- overflow",
	"None", ORBIS32II,},
 
{"l.sfeq", "Set Flag if Equal",
	"The contents of general-purpose register rA and the contents of general-purpose "
	"register rB are compared. If the two registers are equal, "
	"then the compare flag is set; otherwise the compare flag is cleared.",
	"flag <- rA[31:0] == rB[31:0]",
	"flag <- rA[63:0] == rB[63:0]",
	"None", ORBIS32I,},
 
{"l.sfne", "Set Flag if Not Equal",
	"The contents of general-purpose register rA and the contents of general-purpose "
	"register rB are compared. If the two registers are not equal, "
	"then the compare flag is set; otherwise the compare flag is cleared.",
	"flag <- rA[31:0] != rB[31:0]",
	"flag <- rA[63:0] != rB[63:0]",
	"None", ORBIS32I,},
 
{"l.sfgts", "Set Flag if Greater Than Signed",
	"The contents of general-purpose register rA and the contents of general-purpose "
	"register rB are compared as signed integers. If the contents "
	"of the first register are greater than the contents of the second "
	"register, "
	"then the compare flag is set; otherwise the compare flag is cleared.",
	"flag <- rA[31:0] > rB[31:0]",
	"flag <- rA[63:0] > rB[63:0]",
	"None", ORBIS32I,},
 
{"l.sfges", "Set Flag if Greater or Equal Than Signed",
	"The contents of general-purpose register rA and the contents of general-purpose "
	"register rB are compared as signed integers. If the contents "
	"of the first register are greater or equal than the contents of the second "
	"register, "
	"then the compare flag is set; otherwise the compare flag is cleared.",
	"flag <- rA[31:0] >= rB[31:0]",
	"flag <- rA[63:0] >= rB[63:0]",
	"None", ORBIS32I,},
 
{"l.sflts", "Set Flag if Less Than Signed",
	"The contents of general-purpose register rA and the contents of general-purpose "
	"register rB are compared as signed integers. If the contents "
	"of the first register are less than the contents of the second "
	"register, "
	"then the compare flag is set; otherwise the compare flag is cleared.",
	"flag <- rA[31:0] < rB[31:0]",
	"flag <- rA[63:0] < rB[63:0]",
	"None", ORBIS32I,},
 
{"l.sfles", "Set Flag if Less or Equal Than Signed",
	"The contents of general-purpose register rA and the contents of general-purpose "
	"register rB are compared as signed integers. If the contents "
	"of the first register are less or equal than the contents of the second "
	"register, "
	"then the compare flag is set; otherwise the compare flag is cleared.",
	"flag <- rA[31:0] <= rB[31:0]",
	"flag <- rA[63:0] <= rB[63:0]",
	"None", ORBIS32I,},
 
{"l.sfgtu", "Set Flag if Greater Than Unsigned",
	"The contents of general-purpose register rA and the contents of general-purpose "
	"register rB are compared as unsigned integers. If the contents "
	"of the first register are greater than the contents of the second "
	"register, "
	"then the compare flag is set; otherwise the compare flag is cleared.",
	"flag <- rA[31:0] > rB[31:0]",
	"flag <- rA[63:0] > rB[63:0]",
	"None", ORBIS32I,},
 
{"l.sfgeu", "Set Flag if Greater or Equal Than Unsigned",
	"The contents of general-purpose register rA and the contents of general-purpose "
	"register rB are compared as unsigned integers. If the contents "
	"of the first register are greater or equal than the contents of the second "
	"register, "
	"then the compare flag is set; otherwise the compare flag is cleared.",
	"flag <- rA[31:0] >= rB[31:0]",
	"flag <- rA[63:0] >= rB[63:0]",
	"None", ORBIS32I,},
 
{"l.sfltu", "Set Flag if Less Than Unsigned",
	"The contents of general-purpose register rA and the contents of general-purpose "
	"register rB are compared as unsigned integers. If the contents "
	"of the first register are less than the contents of the second "
	"register, "
	"then the compare flag is set; otherwise the compare flag is cleared.",
	"flag <- rA[31:0] < rB[31:0]",
	"flag <- rA[63:0] < rB[63:0]",
	"None", ORBIS32I,},
 
{"l.sfleu", "Set Flag if Less or Equal Than Unsigned",
	"The contents of general-purpose register rA and the contents of general-purpose "
	"register rB are compared as unsigned integers. If the contents "
	"of the first register are less or equal than the contents of the second "
	"register, "
	"then the compare flag is set; otherwise the compare flag is cleared.",
	"flag <- rA[31:0] <= rB[31:0]",
	"flag <- rA[63:0] <= rB[63:0]",
	"None", ORBIS32I,},
 
{"l.sfeqi", "Set Flag if Equal Immediate",
	"The contents of general-purpose register rA and sign-extended immediate "
	"are compared. If the two registers are equal, "
	"then the compare flag is set; otherwise the compare flag is cleared.",
	"flag <- rA[31:0] == rB[31:0]",
	"flag <- rA[63:0] == rB[63:0]",
	"None", ORBIS32II,},
 
{"l.sfnei", "Set Flag if Not Equal Immediate",
	"The contents of general-purpose register rA and "
	"sign-extended immediate are compared. If the two registers are not equal, "
	"then the compare flag is set; otherwise the compare flag is cleared.",
	"flag <- rA[31:0] != rB[31:0]",
	"flag <- rA[63:0] != rB[63:0]",
	"None", ORBIS32II,},
 
{"l.sfgtsi", "Set Flag if Greater Than Immediate Signed",
	"The contents of general-purpose register rA and "
	"sign-extended immediate are compared as signed integers. If the contents "
	"of the first register are greater than the contents of the second "
	"register, "
	"then the compare flag is set; otherwise the compare flag is cleared.",
	"flag <- rA[31:0] > rB[31:0]",
	"flag <- rA[63:0] > rB[63:0]",
	"None", ORBIS32II,},
 
{"l.sfgesi", "Set Flag if Greater or Equal Than Immediate Signed",
	"The contents of general-purpose register rA and "
	"sign-extended immediate are compared as signed integers. If the contents "
	"of the first register are greater or equal than the contents of the second "
	"register, "
	"then the compare flag is set; otherwise the compare flag is cleared.",
	"flag <- rA[31:0] >= rB[31:0]",
	"flag <- rA[63:0] >= rB[63:0]",
	"None", ORBIS32II,},
 
{"l.sfltsi", "Set Flag if Less Than Immediate Signed",
	"The contents of general-purpose register rA and "
	"sign-extended immediate are compared as signed integers. If the contents "
	"of the first register are less than the contents of the second "
	"register, "
	"then the compare flag is set; otherwise the compare flag is cleared.",
	"flag <- rA[31:0] < rB[31:0]",
	"flag <- rA[63:0] < rB[63:0]",
	"None", ORBIS32II,},
 
{"l.sflesi", "Set Flag if Less or Equal Than Immediate Signed",
	"The contents of general-purpose register rA and "
	"sign-extended immediate are compared as signed integers. If the contents "
	"of the first register are less or equal than the contents of the second "
	"register, "
	"then the compare flag is set; otherwise the compare flag is cleared.",
	"flag <- rA[31:0] <= rB[31:0]",
	"flag <- rA[63:0] <= rB[63:0]",
	"None", ORBIS32II,},
 
{"l.sfgtui", "Set Flag if Greater Than Immediate Unsigned",
	"The contents of general-purpose register rA and "
	"zero-extended immediate are compared as unsigned integers. If the contents "
	"of the first register are greater than the contents of the second "
	"register, "
	"then the compare flag is set; otherwise the compare flag is cleared.",
	"flag <- rA[31:0] > rB[31:0]",
	"flag <- rA[63:0] > rB[63:0]",
	"None", ORBIS32II,},
 
{"l.sfgeui", "Set Flag if Greater or Equal Than Immediate Unsigned",
	"The contents of general-purpose register rA and "
	"zero-extended immediate are compared as unsigned integers. If the contents "
	"of the first register are greater or equal than the contents of the second "
	"register, "
	"then the compare flag is set; otherwise the compare flag is cleared.",
	"flag <- rA[31:0] >= rB[31:0]",
	"flag <- rA[63:0] >= rB[63:0]",
	"None", ORBIS32II,},
 
{"l.sfltui", "Set Flag if Less Than Immediate Unsigned",
	"The contents of general-purpose register rA and "
	"zero-extended immediate are compared as unsigned integers. If the contents "
	"of the first register are less than the contents of the second "
	"register, "
	"then the compare flag is set; otherwise the compare flag is cleared.",
	"flag <- rA[31:0] < rB[31:0]",
	"flag <- rA[63:0] < rB[63:0]",
	"None", ORBIS32II,},
 
{"l.sfleui", "Set Flag if Less or Equal Than Immediate Unsigned",
	"The contents of general-purpose register rA and "
	"zero-extended immediate are compared as unsigned integers. If the contents "
	"of the first register are less or equal than the contents of the second "
	"register, "
	"then the compare flag is set; otherwise the compare flag is cleared.",
	"flag <- rA[31:0] <= rB[31:0]",
	"flag <- rA[63:0] <= rB[63:0]",
	"None", ORBIS32II,},
 
{"l.mtspr", "Move To Special-Purpose Register",
	"The contents of general-purpose register rB are moved into special register "
	"identified by the sum of general-purpose register rA and zero-extended immediate.",
	"spr(rA+extz(Immediate)) <- rA[31:0]",
	"spr(rA+extz(Immediate)) <- rA[31:0]",
	"None", ORBIS32I,},
 
{"l.mfspr", "Move From Special-Purpose Register",
	"The contents of special register identified by the sum of general-purpose rA and "
	"zero-extended immediate are moved into general-purpose register rD.",
	"rD[31:0] <- spr(rA+extz(Immediate))",
	"rD[63:0] <- spr(rA+extz(Immediate))",
	"None", ORBIS32I,},
 
{"l.nop", "No Operation",
	"This instruction does not do anything except it takes at least one "
	"clock cycle to complete. It is often used to fill delay slot gaps.",
	"",
	"",
	"None", ORBIS32I,},
 
{"l.movhi", "Move Immediate High",
	"16-bit immediate is zero-extended, shifted left by 16 bits and placed "
	"into general-purpose register rD.",
	"rA[31:0] <- extz(Immediate) << 16",
	"rA[63:0] <- extz(Immediate) << 16",
	"None", ORBIS32I,},
 
{"l.bf", "Branch if Flag",
	"The immediate is shifted left two bits, sign-extended to "
	"program counter width and then added to the address of the delay slot. The result "
	"is effective address of the branch. If the compare flag is set, "
	"then the program branches "
	"to EA with a delay of one instruction.",
	"EA <- (Immediate || 00) + DelayInsnAddr\\PC <- EA if flag set",
	"EA <- (Immediate || 00) + DelayInsnAddr\\PC <- EA if flag set",
	"None", ORBIS32I,},
 
{"l.bnf", "Branch if No Flag",
	"The immediate is shifted left two bits, sign-extended to "
	"program counter width and then added to the address of the delay slot. The result "
	"is effective address of the branch. If the compare flag is cleared, "
	"then the program branches "
	"to EA with a delay of one instruction.",
	"EA <- (Immediate || 00) + DelayInsnAddr\\PC <- EA if flag cleared",
	"EA <- (Immediate || 00) + DelayInsnAddr\\PC <- EA if flag cleared",
	"None", ORBIS32I,},
 
{"l.jal", "Jump and Link",
	"The immediate is shifted left two bits, sign-extended to "
	"program counter width and then added to the address of the delay slot. The result "
	"is effective address of the jump. The program unconditionally jumps "
	"to EA with a delay of one instruction. The "
	"address of the instruction after the delay slot is placed in the "
	"link register. ",
	"PC <- (Immediate || 00) + DelayInsnAddr\\LR <- DelayInsnAddr + 4",
	"PC <- (Immediate || 00) + DelayInsnAddr\\LR <- DelayInsnAddr + 4",
	"None", ORBIS32I,},
 
{"l.j", "Jump",
	"The immediate is shifted left two bits, sign-extended to "
	"program counter width and then added to the address of the delay slot. The result "
	"is effective address of the jump. The program unconditionally jumps "
	"to EA with a delay of one instruction.",
	"PC <- (Immediate || 00) + DelayInsnAddr\\LR <- DelayInsnAddr + 4",
	"PC <- (Immediate || 00) + DelayInsnAddr\\LR <- DelayInsnAddr + 4",
	"None", ORBIS32I,},
 
{"l.jalr", "Jump and Link Register",
	"The contents of general-purpose register rB "
	"is effective address of the jump. The program unconditionally jumps "
	"to EA with a delay of one instruction. The "
	"address of the instruction after the delay slot is placed in the "
	"link register.",
	"PC <- rB\\LR <- DelayInsnAddr + 4",
	"PC <- rB\\LR <- DelayInsnAddr + 4",
	"None", ORBIS32I,},
 
{"l.jr", "Jump Register",
	"The contents of general-purpose register rB "
	"is effective address of the jump. The program unconditionally jumps "
	"to EA with a delay of one instruction.",
	"PC <- rB",
	"PC <- rB",
	"None", ORBIS32I,},
 
{"l.sys", "System Call",
	"Execution of system call instruction results in the system call "
	"exception. System calls exception is a request to the operating system "
	"to provide operating system services. Immediate specifies which system service "
	"is required.",
	"system-call-exception(K)",
	"system-call-exception(K)",
	"None", ORBIS32I,},
 
{"l.brk", "Breakpoint",
	"Execution of the breakpoint instruction results in the breakpoint "
	"exception. Breakpoint exception is a request to the operating system "
	"and to the debug facility to execute certain debug services. "
	"Immediate is used by the debug to identify which breakpoint it is. ",
	"breakpoint-exception(K)",
	"breakpoint-exception(K)",
	"None", ORBIS32I,},
 
{"l.msync", "Memory Syncronization",
	"Execution of memory synchronization instruction results in completion "
	"of all load/store operations before the RISC core continues.",
	"memory-synchronization",
	"memory-synchronization",
	"None", ORBIS32II,},
 
{"l.psync", "Pipeline Syncronization",
	"Execution of pipeline synchronization instruction results in completion "
	"of all instructions that were fetched before l.psync instruction. Once all "
	"instructions are completed, instructions fetched after l.psync are flushed from the "
	" pipeline and fetched again.",
	"pipeline-synchronization",
	"pipeline-synchronization",
	"None", ORBIS32II,},
 
{"l.csync", "Context Syncronization",
	"Execution of context synchronization instruction results in completion "
	"of all operations inside RISC and flush of the instruction pipelines. "
	"When all operations are complete, RISC core resumes with empty instruction pipeline and "
	"fresh context in all units (MMU for example).",
	"context-synchronization",
	"context-synchronization",
	"None", ORBIS32II,},
 
{"l.rfe", "Return From Exception",
	"Execution of this instruction restores the state of the processor prior to "
	"the exception.",
	"state_restore()",
	"state_restore()",
	"None", ORBIS32I,},
 
{"l.cust1", "Reserved for ORBIS32/64 Custom Instructions",
	"This fake instruction only allocates instruction set space for custom instructions. "
	"Custom instructions are those that are not defined by the architecture, but instead "
	"by the implementation itself.",
	"N/A",
	"N/A",
	"N/A", ORBIS32II,},
 
{"l.cust2", "Reserved for ORBIS32/64 Custom Instructions",
	"This fake instruction only allocates instruction set space for custom instructions. "
	"Custom instructions are those that are not defined by the architecture, but instead "
	"by the implementation itself.",
	"N/A",
	"N/A",
	"N/A", ORBIS32II,},
 
{"l.cust3", "Reserved for ORBIS32/64 Custom Instructions",
	"This fake instruction only allocates instruction set space for custom instructions. "
	"Custom instructions are those that are not defined by the architecture, but instead "
	"by the implementation itself.",
	"N/A",
	"N/A",
	"N/A", ORBIS32II,},
 
{"l.cust4", "Reserved for ORBIS32/64 Custom Instructions",
	"This fake instruction only allocates instruction set space for custom instructions. "
	"Custom instructions are those that are not defined by the architecture, but instead "
	"by the implementation itself.",
	"N/A",
	"N/A",
	"N/A", ORBIS32II,},
 
{"l.cust5", "Reserved for ORBIS32/64 Custom Instructions",
	"This fake instruction only allocates instruction set space for custom instructions. "
	"Custom instructions are those that are not defined by the architecture, but instead "
	"by the implementation itself.",
	"N/A",
	"N/A",
	"N/A", ORBIS32II,},
 
{"l.cust6", "Reserved for ORBIS32/64 Custom Instructions",
	"This fake instruction only allocates instruction set space for custom instructions. "
	"Custom instructions are those that are not defined by the architecture, but instead "
	"by the implementation itself.",
	"N/A",
	"N/A",
	"N/A", ORBIS32II,},
 
{"l.cust7", "Reserved for ORBIS32/64 Custom Instructions",
	"This fake instruction only allocates instruction set space for custom instructions. "
	"Custom instructions are those that are not defined by the architecture, but instead "
	"by the implementation itself.",
	"N/A",
	"N/A",
	"N/A", ORBIS32II,},
 
{"l.cust8", "Reserved for ORBIS32/64 Custom Instructions",
	"This fake instruction only allocates instruction set space for custom instructions. "
	"Custom instructions are those that are not defined by the architecture, but instead "
	"by the implementation itself.",
	"N/A",
	"N/A",
	"N/A", ORBIS32II,},
 
/*** ORFPX32 ***/
 
{"lf.add.s", "Add Floating-Point Single-Precision",
	"The contents of vector/floating-point register vfrA is added to the contents "
	"of vector/floating-point register vfrB to form the result. The result is placed into "
	"vector/floating-point register vfrD.",
	"vfrD[31:0] <- vfrA[31:0] + vfrB[31:0]",
	"",
	"", ORFPX32I,},
 
{"lf.sub.s", "Subtract Floating-Point Single-Precision",
	"The contents of vector/floating-point register vfrB is subtracted from the contents "
	"of vector/floating-point register vfrA to form the result. The result is placed into "
	"vector/floating-point register vfrD.",
	"vfrD[31:0] <- vfrA[31:0] - vfrB[31:0]",
	"",
	"", ORFPX32I,},
 
{"lf.mul.s", "Multiply Floating-Point Single-Precision",
	"The contents of vector/floating-point register vfrA is multiplied by the contents "
	"of vector/floating-point register vfrB to form the result. The result is placed into "
	"vector/floating-point register vfrD.",
	"vfrD[31:0] <- vfrA[31:0] * vfrB[31:0]",
	"",
	"", ORFPX32I,},
 
{"lf.div.s", "Divide Floating-Point Single-Precision",
	"The contents of vector/floating-point register vfrA is divided by the contents "
	"of vector/floating-point register vfrB to form the result. The result is placed into "
	"vector/floating-point register vfrD.",
	"vfrD[31:0] <- vfrA[31:0] / vfrB[31:0]",
	"",
	"", ORFPX32II,},
 
{"lf.rem.s", "Remainder Floating-Point Single-Precision",
	"The contents of vector/floating-point register vfrA is divided by the contents "
	"of vector/floating-point register vfrB and remainder is used as the result. The result is placed into "
	"vector/floating-point register vfrD.",
	"vfrD[31:0] <- vfrA[31:0] % vfrB[31:0]",
	"",
	"", ORFPX32II,},
 
{"lf.madd.s", "Multiply and Add Floating-Point Single-Precision",
	"The contents of vector/floating-point register vfrA is multiplied by the contents "
	"of vector/floating-point register vfrB and added to special-purpose register "
	"FPMADDLO/FPMADDHI.",
	"FPMADDHI[31:0]FPMADDLO[31:0] <- vfrA[31:0] * vfrB[31:0] + FPMADDHI[31:0]FPMADDLO[31:0]",
	"",
	"", ORFPX32II,},
 
{"lf.sfeq.s", "Set Flag if Equal Floating-Point Single-Precision",
	"The contents of vector/floating-point register vfrA and the contents of "
	"vector/floating-point register vfrB are compared. If the two registers are equal, "
	"then the compare flag is set; otherwise the compare flag is cleared.",
	"flag <- vfrA[31:0] == vfrB[31:0]",
	"",
	"None", ORFPX32I,},
 
{"lf.sfne.s", "Set Flag if Not Equal Floating-Point Single-Precision",
	"The contents of vector/floating-point register vfrA and the contents of "
	"vector/floating-point register vfrB are compared. If the two registers are not equal, "
	"then the compare flag is set; otherwise the compare flag is cleared.",
	"flag <- vfrA[31:0] != vfrB[31:0]",
	"",
	"None", ORFPX32I,},
 
{"lf.sfgt.s", "Set Flag if Greater Than Floating-Point Single-Precision",
	"The contents of vector/floating-point register vfrA and the contents of "
	"vector/floating-point register vfrB are compared. If first register is greater than "
	"second register, then the compare flag is set; otherwise the compare flag is cleared.",
	"flag <- vfrA[31:0] > vfrB[31:0]",
	"",
	"None", ORFPX32I,},
 
{"lf.sfge.s", "Set Flag if Greater or Equal Than Floating-Point Single-Precision",
	"The contents of vector/floating-point register vfrA and the contents of "
	"vector/floating-point register vfrB are compared. If first register is greater "
	"or equal than the second register, then the compare flag is set; otherwise the compare flag is cleared.",
	"flag <- vfrA[31:0] >= vfrB[31:0]",
	"",
	"None", ORFPX32I,},
 
{"lf.sflt.s", "Set Flag if Less Than Floating-Point Single-Precision",
	"The contents of vector/floating-point register vfrA and the contents of "
	"vector/floating-point register vfrB are compared. If first register is less than "
	"second register, then the compare flag is set; otherwise the compare flag is cleared.",
	"flag <- vfrA[31:0] < vfrB[31:0]",
	"",
	"None", ORFPX32I,},
 
{"lf.sfle.s", "Set Flag if Less or Equal Than Floating-Point Single-Precision",
	"The contents of vector/floating-point register vfrA and the contents of "
	"vector/floating-point register vfrB are compared. If first register is less "
	"or equal than the second register, then the compare flag is set; otherwise the compare flag is cleared.",
	"flag <- vfrA[31:0] <= vfrB[31:0]",
	"",
	"None", ORFPX32I,},
 
{"lf.ftoi.s", "Floating-Point Single-Precision To Integer",
	"The contents of vector/floating-point register vfrA are converted to integer "
	"and stored into general-purpose register rD.",
	"rD[31:0] <- ftoi(vfrA[31:0])",
	"",
	"None", ORFPX32I,},
 
{"lf.itof.s", "Integer To Floating-Point Single-Precision",
	"The contents of general-purpose register rA are converted to single-precision "
	"floating-point number and stored into vector/floating-point register vfrD.",
	"vfrD[31:0] <- itof(rA[31:0])",
	"",
	"None", ORFPX32I,},
 
{"lf.cust1.s", "Reserved for ORFPX32 Custom Instructions",
	"This fake instruction only allocates instruction set space for custom instructions. "
	"Custom instructions are those that are not defined by the architecture, but instead "
	"by the implementation itself.",
	"N/A",
	"N/A",
	"N/A", ORFPX32II,},
 
/*** ORFPX64 ***/
 
{"lf.add.d", "Add Floating-Point Double-Precision",
	"The contents of vector/floating-point register vfrA is added to the contents "
	"of vector/floating-point register vfrB to form the result. The result is placed into "
	"vector/floating-point register vfrD.",
	"",
	"vfrD[63:0] <- vfrA[63:0] + vfrB[63:0]",
	"", ORFPX64I,},
 
{"lf.sub.d", "Subtract Floating-Point Double-Precision",
	"The contents of vector/floating-point register vfrB is subtracted from the contents "
	"of vector/floating-point register vfrA to form the result. The result is placed into "
	"vector/floating-point register vfrD.",
	"",
	"vfrD[63:0] <- vfrA[63:0] - vfrB[63:0]",
	"", ORFPX64I,},
 
{"lf.mul.d", "Multiply Floating-Point Double-Precision",
	"The contents of vector/floating-point register vfrA is multiplied by the contents "
	"of vector/floating-point register vfrB to form the result. The result is placed into "
	"vector/floating-point register vfrD.",
	"",
	"vfrD[63:0] <- vfrA[63:0] * vfrB[63:0]",
	"", ORFPX64I,},
 
{"lf.div.d", "Divide Floating-Point Double-Precision",
	"The contents of vector/floating-point register vfrA is divided by the contents "
	"of vector/floating-point register vfrB to form the result. The result is placed into "
	"vector/floating-point register vfrD.",
	"",
	"vfrD[63:0] <- vfrA[63:0] / vfrB[63:0]",
	"", ORFPX64II,},
 
{"lf.rem.d", "Remainder Floating-Point Double-Precision",
	"The contents of vector/floating-point register vfrA is divided by the contents "
	"of vector/floating-point register vfrB and remainder is used as the result. The result is placed into "
	"vector/floating-point register vfrD.",
	"",
	"vfrD[63:0] <- vfrA[63:0] % vfrB[63:0]",
	"", ORFPX64II,},
 
{"lf.madd.d", "Multiply and Add Floating-Point Double-Precision",
	"The contents of vector/floating-point register vfrA is multiplied by the contents "
	"of vector/floating-point register vfrB and added to special-purpose register "
	"FPMADDLO/FPMADDHI.",
	"",
	"FPMADDHI[31:0]FPMADDLO[31:0] <- vfrA[63:0] * vfrB[63:0] + FPMADDHI[31:0]FPMADDLO[31:0]",
	"", ORFPX64II,},
 
{"lf.sfeq.d", "Set Flag if Equal Floating-Point Double-Precision",
	"The contents of vector/floating-point register vfrA and the contents of "
	"vector/floating-point register vfrB are compared. If the two registers are equal, "
	"then the compare flag is set; otherwise the compare flag is cleared.",
	"",
	"flag <- vfrA[63:0] == vfrB[63:0]",
	"None", ORFPX64I,},
 
{"lf.sfne.d", "Set Flag if Not Equal Floating-Point Double-Precision",
	"The contents of vector/floating-point register vfrA and the contents of "
	"vector/floating-point register vfrB are compared. If the two registers are not equal, "
	"then the compare flag is set; otherwise the compare flag is cleared.",
	"",
	"flag <- vfrA[63:0] != vfrB[63:0]",
	"None", ORFPX64I,},
 
{"lf.sfgt.d", "Set Flag if Greater Than Floating-Point Double-Precision",
	"The contents of vector/floating-point register vfrA and the contents of "
	"vector/floating-point register vfrB are compared. If first register is greater than "
	"second register, then the compare flag is set; otherwise the compare flag is cleared.",
	"",
	"flag <- vfrA[63:0] > vfrB[63:0]",
	"None", ORFPX64I,},
 
{"lf.sfge.d", "Set Flag if Greater or Equal Than Floating-Point Double-Precision",
	"The contents of vector/floating-point register vfrA and the contents of "
	"vector/floating-point register vfrB are compared. If first register is greater "
	"or equal than the second register, then the compare flag is set; otherwise the compare flag is cleared.",
	"",
	"flag <- vfrA[63:0] >= vfrB[63:0]",
	"None", ORFPX64I,},
 
{"lf.sflt.d", "Set Flag if Less Than Floating-Point Double-Precision",
	"The contents of vector/floating-point register vfrA and the contents of "
	"vector/floating-point register vfrB are compared. If first register is less than "
	"second register, then the compare flag is set; otherwise the compare flag is cleared.",
	"",
	"flag <- vfrA[63:0] < vfrB[63:0]",
	"None", ORFPX64I,},
 
{"lf.sfle.d", "Set Flag if Less or Equal Than Floating-Point Double-Precision",
	"The contents of vector/floating-point register vfrA and the contents of "
	"vector/floating-point register vfrB are compared. If first register is less "
	"or equal than the second register, then the compare flag is set; otherwise the compare flag is cleared.",
	"",
	"flag <- vfrA[363:0] <= vfrB[63:0]",
	"None", ORFPX64I,},
 
{"lf.ftoi.d", "Floating-Point Double-Precision To Integer",
	"The contents of vector/floating-point register vfrA are converted to integer "
	"and stored into general-purpose register rD.",
	"",
	"rD[63:0] <- ftoi(vfrA[63:0])",
	"None", ORFPX64I,},
 
{"lf.itof.d", "Integer To Floating-Point Double-Precision",
	"The contents of general-purpose register rA are converted to Double-precision "
	"floating-point number and stored into vector/floating-point register vfrD.",
	"",
	"vfrD[63:0] <- itof(rA[63:0])",
	"None", ORFPX64I,},
 
{"lf.cust1.d", "Reserved for ORFPX64 Custom Instructions",
	"This fake instruction only allocates instruction set space for custom instructions. "
	"Custom instructions are those that are not defined by the architecture, but instead "
	"by the implementation itself.",
	"N/A",
	"N/A",
	"N/A", ORFPX64II,},
 
/*** ORVDX64 ***/
 
{"lv.all_eq.b", "Vector Byte Elements All Equal",
	"All byte elements of vector/floating-point register vfrA are compared "
	"to byte elements of vector/floating-point register vfrB. Compare flag is "
	"set if all corresponding elements are equal; otherwise compare flag is cleared. "
	"\\Compare flag is replicated into all bit positions of vector/floating-point "
	"register vfrD.",
	"",
	"flag <- vfrA[7:0] == vfrB[7:0] \\"
	"\tvfrA[15:8] == vfrB[15:8] \\"
	"\tvfrA[23:16] == vfrB[23:16] \\"
	"\tvfrA[31:24] == vfrB[31:24] \\"
	"\tvfrA[39:32] == vfrB[39:32] \\"
	"\tvfrA[47:40] == vfrB[47:40] \\"
	"\tvfrA[55:48] == vfrB[55:48] \\"
	"\tvfrA[63:56] == vfrB[63:56]"
	"vfrD[63:0] <- repl(flag)",
	"None", ORVDX64I,},
 
{"lv.all_eq.h", "Vector Half-Word Elements All Equal",
	"All half-word elements of vector/floating-point register vfrA are compared "
	"to half-word elements of vector/floating-point register vfrB. Compare flag is "
	"set if all corresponding elements are equal; otherwise compare flag is cleared. "
	"\\Compare flag is replicated into all bit positions of vector/floating-point "
	"register vfrD.",
	"",
	"flag <- vfrA[15:0] == vfrB[15:0] \\"
	"\tvfrA[31:16] == vfrB[31:16] \\"
	"\tvfrA[47:32] == vfrB[47:32] \\"
	"\tvfrA[63:48] == vfrB[63:48]"
	"vfrD[63:0] <- repl(flag)",
	"None", ORVDX64I,},
 
{"lv.all_ge.b", "Vector Byte Elements All Greater or Equal Than",
	"All byte elements of vector/floating-point register vfrA are compared "
	"to byte elements of vector/floating-point register vfrB. Compare flag is "
	"set if all elements of vfrA are greater or equal than elements of vfrB;"
	"otherwise compare flag is cleared. "
	"\\Compare flag is replicated into all bit positions of vector/floating-point "
	"register vfrD.",
	"",
	"flag <- vfrA[7:0] >= vfrB[7:0] \\"
	"\tvfrA[15:8] >= vfrB[15:8] \\"
	"\tvfrA[23:16] >= vfrB[23:16] \\"
	"\tvfrA[31:24] >= vfrB[31:24] \\"
	"\tvfrA[39:32] >= vfrB[39:32] \\"
	"\tvfrA[47:40] >= vfrB[47:40] \\"
	"\tvfrA[55:48] >= vfrB[55:48] \\"
	"\tvfrA[63:56] >= vfrB[63:56]"
	"vfrD[63:0] <- repl(flag)",
	"None", ORVDX64I,},
 
{"lv.all_ge.h", "Vector Half-Word Elements All Greater or Equal Than",
	"All half-word elements of vector/floating-point register vfrA are compared "
	"to half-word elements of vector/floating-point register vfrB. Compare flag is "
	"set if all elements of vfrA are greater or equal than elements of vfrB;"
	"otherwise compare flag is cleared. "
	"\\Compare flag is replicated into all bit positions of vector/floating-point "
	"register vfrD.",
	"",
	"flag <- vfrA[15:0] >= vfrB[15:0] \\"
	"\tvfrA[31:16] >= vfrB[31:16] \\"
	"\tvfrA[47:32] >= vfrB[47:32] \\"
	"\tvfrA[63:48] >= vfrB[63:48]"
	"vfrD[63:0] <- repl(flag)",
	"None", ORVDX64I,},
 
{"lv.all_gt.b", "Vector Byte Elements All Greater Than",
	"All byte elements of vector/floating-point register vfrA are compared "
	"to byte elements of vector/floating-point register vfrB. Compare flag is "
	"set if all elements of vfrA are greater than elements of vfrB;"
	"otherwise compare flag is cleared. "
	"\\Compare flag is replicated into all bit positions of vector/floating-point "
	"register vfrD.",
	"",
	"flag <- vfrA[7:0] > vfrB[7:0] \\"
	"\tvfrA[15:8] > vfrB[15:8] \\"
	"\tvfrA[23:16] > vfrB[23:16] \\"
	"\tvfrA[31:24] > vfrB[31:24] \\"
	"\tvfrA[39:32] > vfrB[39:32] \\"
	"\tvfrA[47:40] > vfrB[47:40] \\"
	"\tvfrA[55:48] > vfrB[55:48] \\"
	"\tvfrA[63:56] > vfrB[63:56]"
	"vfrD[63:0] <- repl(flag)",
	"None", ORVDX64I,},
 
{"lv.all_gt.h", "Vector Half-Word Elements All Greater Than",
	"All half-word elements of vector/floating-point register vfrA are compared "
	"to half-word elements of vector/floating-point register vfrB. Compare flag is "
	"set if all elements of vfrA are greater than elements of vfrB;"
	"otherwise compare flag is cleared. "
	"\\Compare flag is replicated into all bit positions of vector/floating-point "
	"register vfrD.",
	"",
	"flag <- vfrA[15:0] > vfrB[15:0] \\"
	"\tvfrA[31:16] > vfrB[31:16] \\"
	"\tvfrA[47:32] > vfrB[47:32] \\"
	"\tvfrA[63:48] > vfrB[63:48]"
	"vfrD[63:0] <- repl(flag)",
	"None", ORVDX64I,},
 
{"lv.all_lt.b", "Vector Byte Elements All Less Than",
	"All byte elements of vector/floating-point register vfrA are compared "
	"to byte elements of vector/floating-point register vfrB. Compare flag is "
	"set if all elements of vfrA are less than elements of vfrB;"
	"otherwise compare flag is cleared. "
	"\\Compare flag is replicated into all bit positions of vector/floating-point "
	"register vfrD.",
	"",
	"flag <- vfrA[7:0] < vfrB[7:0] \\"
	"\tvfrA[15:8] < vfrB[15:8] \\"
	"\tvfrA[23:16] < vfrB[23:16] \\"
	"\tvfrA[31:24] < vfrB[31:24] \\"
	"\tvfrA[39:32] < vfrB[39:32] \\"
	"\tvfrA[47:40] < vfrB[47:40] \\"
	"\tvfrA[55:48] < vfrB[55:48] \\"
	"\tvfrA[63:56] < vfrB[63:56]"
	"vfrD[63:0] <- repl(flag)",
	"None", ORVDX64I,},
 
{"lv.all_lt.h", "Vector Half-Word Elements All Less Than",
	"All half-word elements of vector/floating-point register vfrA are compared "
	"to half-word elements of vector/floating-point register vfrB. Compare flag is "
	"set if all elements of vfrA are less than elements of vfrB;"
	"otherwise compare flag is cleared. "
	"\\Compare flag is replicated into all bit positions of vector/floating-point "
	"register vfrD.",
	"",
	"flag <- vfrA[15:0] < vfrB[15:0] \\"
	"\tvfrA[31:16] < vfrB[31:16] \\"
	"\tvfrA[47:32] < vfrB[47:32] \\"
	"\tvfrA[63:48] < vfrB[63:48]"
	"vfrD[63:0] <- repl(flag)",
	"None", ORVDX64I,},
 
{"lv.all_le.b", "Vector Byte Elements All Less or Equal Than",
	"All byte elements of vector/floating-point register vfrA are compared "
	"to byte elements of vector/floating-point register vfrB. Compare flag is "
	"set if all elements of vfrA are less or equal than elements of vfrB;"
	"otherwise compare flag is cleared. "
	"\\Compare flag is replicated into all bit positions of vector/floating-point "
	"register vfrD.",
	"",
	"flag <- vfrA[7:0] <= vfrB[7:0] \\"
	"\tvfrA[15:8] <= vfrB[15:8] \\"
	"\tvfrA[23:16] <= vfrB[23:16] \\"
	"\tvfrA[31:24] <= vfrB[31:24] \\"
	"\tvfrA[39:32] <= vfrB[39:32] \\"
	"\tvfrA[47:40] <= vfrB[47:40] \\"
	"\tvfrA[55:48] <= vfrB[55:48] \\"
	"\tvfrA[63:56] <= vfrB[63:56]"
	"vfrD[63:0] <- repl(flag)",
	"None", ORVDX64I,},
 
{"lv.all_le.h", "Vector Half-Word Elements All Less or Equal Than",
	"All half-word elements of vector/floating-point register vfrA are compared "
	"to half-word elements of vector/floating-point register vfrB. Compare flag is "
	"set if all elements of vfrA are less or equal than elements of vfrB;"
	"otherwise compare flag is cleared. "
	"\\Compare flag is replicated into all bit positions of vector/floating-point "
	"register vfrD.",
	"",
	"flag <- vfrA[15:0] ,= vfrB[15:0] \\"
	"\tvfrA[31:16] <= vfrB[31:16] \\"
	"\tvfrA[47:32] <= vfrB[47:32] \\"
	"\tvfrA[63:48] <= vfrB[63:48]"
	"vfrD[63:0] <- repl(flag)",
	"None", ORVDX64I,},
 
{"lv.all_ne.b", "Vector Byte Elements All Not Equal",
	"All byte elements of vector/floating-point register vfrA are compared "
	"to byte elements of vector/floating-point register vfrB. Compare flag is "
	"set if all corresponding elements are not equal; otherwise compare flag is cleared. "
	"\\Compare flag is replicated into all bit positions of vector/floating-point "
	"register vfrD.",
	"",
	"flag <- vfrA[7:0] != vfrB[7:0] \\"
	"\tvfrA[15:8] != vfrB[15:8] \\"
	"\tvfrA[23:16] != vfrB[23:16] \\"
	"\tvfrA[31:24] != vfrB[31:24] \\"
	"\tvfrA[39:32] != vfrB[39:32] \\"
	"\tvfrA[47:40] != vfrB[47:40] \\"
	"\tvfrA[55:48] != vfrB[55:48] \\"
	"\tvfrA[63:56] != vfrB[63:56]"
	"vfrD[63:0] <- repl(flag)",
	"None", ORVDX64I,},
 
{"lv.all_ne.h", "Vector Half-Word Elements All Not Equal",
	"All half-word elements of vector/floating-point register vfrA are compared "
	"to half-word elements of vector/floating-point register vfrB. Compare flag is "
	"set if all corresponding elements are not equal; otherwise compare flag is cleared. "
	"\\Compare flag is replicated into all bit positions of vector/floating-point "
	"register vfrD.",
	"",
	"flag <- vfrA[15:0] != vfrB[15:0] \\"
	"\tvfrA[31:16] != vfrB[31:16] \\"
	"\tvfrA[47:32] != vfrB[47:32] \\"
	"\tvfrA[63:48] != vfrB[63:48]"
	"vfrD[63:0] <- repl(flag)",
	"None", ORVDX64I,},
 
{"lv.any_eq.b", "Vector Byte Elements Any Equal",
	"All byte elements of vector/floating-point register vfrA are compared "
	"to byte elements of vector/floating-point register vfrB. Compare flag is "
	"set if any two corresponding elements are equal; otherwise compare flag is cleared. "
	"\\Compare flag is replicated into all bit positions of vector/floating-point "
	"register vfrD.",
	"",
	"flag <- vfrA[7:0] == vfrB[7:0] ||\\"
	"\tvfrA[15:8] == vfrB[15:8] ||\\"
	"\tvfrA[23:16] == vfrB[23:16] ||\\"
	"\tvfrA[31:24] == vfrB[31:24] ||\\"
	"\tvfrA[39:32] == vfrB[39:32] ||\\"
	"\tvfrA[47:40] == vfrB[47:40] ||\\"
	"\tvfrA[55:48] == vfrB[55:48] ||\\"
	"\tvfrA[63:56] == vfrB[63:56]"
	"vfrD[63:0] <- repl(flag)",
	"None", ORVDX64I,},
 
{"lv.any_eq.h", "Vector Half-Word Elements Any Equal",
	"All half-word elements of vector/floating-point register vfrA are compared "
	"to half-word elements of vector/floating-point register vfrB. Compare flag is "
	"set if any two corresponding elements are equal; otherwise compare flag is cleared. "
	"\\Compare flag is replicated into all bit positions of vector/floating-point "
	"register vfrD.",
	"",
	"flag <- vfrA[15:0] == vfrB[15:0] ||\\"
	"\tvfrA[31:16] == vfrB[31:16] ||\\"
	"\tvfrA[47:32] == vfrB[47:32] ||\\"
	"\tvfrA[63:48] == vfrB[63:48]"
	"vfrD[63:0] <- repl(flag)",
	"None", ORVDX64I,},
 
{"lv.any_ge.b", "Vector Byte Elements Any Greater or Equal Than",
	"All byte elements of vector/floating-point register vfrA are compared "
	"to byte elements of vector/floating-point register vfrB. Compare flag is "
	"set if any element of vfrA is greater or equal than corresponding element of vfrB;"
	"otherwise compare flag is cleared. "
	"\\Compare flag is replicated into all bit positions of vector/floating-point "
	"register vfrD.",
	"",
	"flag <- vfrA[7:0] >= vfrB[7:0] ||\\"
	"\tvfrA[15:8] >= vfrB[15:8] ||\\"
	"\tvfrA[23:16] >= vfrB[23:16] ||\\"
	"\tvfrA[31:24] >= vfrB[31:24] ||\\"
	"\tvfrA[39:32] >= vfrB[39:32] ||\\"
	"\tvfrA[47:40] >= vfrB[47:40] ||\\"
	"\tvfrA[55:48] >= vfrB[55:48] ||\\"
	"\tvfrA[63:56] >= vfrB[63:56]"
	"vfrD[63:0] <- repl(flag)",
	"None", ORVDX64I,},
 
{"lv.any_ge.h", "Vector Half-Word Elements Any Greater or Equal Than",
	"All half-word elements of vector/floating-point register vfrA are compared "
	"to half-word elements of vector/floating-point register vfrB. Compare flag is "
	"set if any element of vfrA is greater or equal than corresponding element of vfrB;"
	"otherwise compare flag is cleared. "
	"\\Compare flag is replicated into all bit positions of vector/floating-point "
	"register vfrD.",
	"",
	"flag <- vfrA[15:0] >= vfrB[15:0] ||\\"
	"\tvfrA[31:16] >= vfrB[31:16] ||\\"
	"\tvfrA[47:32] >= vfrB[47:32] ||\\"
	"\tvfrA[63:48] >= vfrB[63:48]"
	"vfrD[63:0] <- repl(flag)",
	"None", ORVDX64I,},
 
{"lv.any_gt.b", "Vector Byte Elements Any Greater Than",
	"All byte elements of vector/floating-point register vfrA are compared "
	"to byte elements of vector/floating-point register vfrB. Compare flag is "
	"set if any element of vfrA is greater than corresponding element of vfrB;"
	"otherwise compare flag is cleared. "
	"\\Compare flag is replicated into all bit positions of vector/floating-point "
	"register vfrD.",
	"",
	"flag <- vfrA[7:0] > vfrB[7:0] ||\\"
	"\tvfrA[15:8] > vfrB[15:8] ||\\"
	"\tvfrA[23:16] > vfrB[23:16] ||\\"
	"\tvfrA[31:24] > vfrB[31:24] ||\\"
	"\tvfrA[39:32] > vfrB[39:32] ||\\"
	"\tvfrA[47:40] > vfrB[47:40] ||\\"
	"\tvfrA[55:48] > vfrB[55:48] ||\\"
	"\tvfrA[63:56] > vfrB[63:56]"
	"vfrD[63:0] <- repl(flag)",
	"None", ORVDX64I,},
 
{"lv.any_gt.h", "Vector Half-Word Elements Any Greater Than",
	"All half-word elements of vector/floating-point register vfrA are compared "
	"to half-word elements of vector/floating-point register vfrB. Compare flag is "
	"set if any element of vfrA is greater than corresponding element of vfrB;"
	"otherwise compare flag is cleared. "
	"\\Compare flag is replicated into all bit positions of vector/floating-point "
	"register vfrD.",
	"",
	"flag <- vfrA[15:0] > vfrB[15:0] ||\\"
	"\tvfrA[31:16] > vfrB[31:16] ||\\"
	"\tvfrA[47:32] > vfrB[47:32] ||\\"
	"\tvfrA[63:48] > vfrB[63:48]"
	"vfrD[63:0] <- repl(flag)",
	"None", ORVDX64I,},
 
{"lv.any_lt.b", "Vector Byte Elements Any Less Than",
	"All byte elements of vector/floating-point register vfrA are compared "
	"to byte elements of vector/floating-point register vfrB. Compare flag is "
	"set if any element of vfrA is less than corresponding element of vfrB;"
	"otherwise compare flag is cleared. "
	"\\Compare flag is replicated into all bit positions of vector/floating-point "
	"register vfrD.",
	"",
	"flag <- vfrA[7:0] < vfrB[7:0] ||\\"
	"\tvfrA[15:8] < vfrB[15:8] ||\\"
	"\tvfrA[23:16] < vfrB[23:16] ||\\"
	"\tvfrA[31:24] < vfrB[31:24] ||\\"
	"\tvfrA[39:32] < vfrB[39:32] ||\\"
	"\tvfrA[47:40] < vfrB[47:40] ||\\"
	"\tvfrA[55:48] < vfrB[55:48] ||\\"
	"\tvfrA[63:56] < vfrB[63:56]"
	"vfrD[63:0] <- repl(flag)",
	"None", ORVDX64I,},
 
{"lv.any_lt.h", "Vector Half-Word Elements Any Less Than",
	"All half-word elements of vector/floating-point register vfrA are compared "
	"to half-word elements of vector/floating-point register vfrB. Compare flag is "
	"set if any element of vfrA is less than corresponding element of vfrB;"
	"otherwise compare flag is cleared. "
	"\\Compare flag is replicated into all bit positions of vector/floating-point "
	"register vfrD.",
	"",
	"flag <- vfrA[15:0] < vfrB[15:0] ||\\"
	"\tvfrA[31:16] < vfrB[31:16] ||\\"
	"\tvfrA[47:32] < vfrB[47:32] ||\\"
	"\tvfrA[63:48] < vfrB[63:48]"
	"vfrD[63:0] <- repl(flag)",
	"None", ORVDX64I,},
 
{"lv.any_le.b", "Vector Byte Elements Any Less or Equal Than",
	"All byte elements of vector/floating-point register vfrA are compared "
	"to byte elements of vector/floating-point register vfrB. Compare flag is "
	"set if any element of vfrA is less or equal than corresponding element of vfrB;"
	"otherwise compare flag is cleared. "
	"\\Compare flag is replicated into all bit positions of vector/floating-point "
	"register vfrD.",
	"",
	"flag <- vfrA[7:0] <= vfrB[7:0] ||\\"
	"\tvfrA[15:8] <= vfrB[15:8] ||\\"
	"\tvfrA[23:16] <= vfrB[23:16] ||\\"
	"\tvfrA[31:24] <= vfrB[31:24] ||\\"
	"\tvfrA[39:32] <= vfrB[39:32] ||\\"
	"\tvfrA[47:40] <= vfrB[47:40] ||\\"
	"\tvfrA[55:48] <= vfrB[55:48] ||\\"
	"\tvfrA[63:56] <= vfrB[63:56]"
	"vfrD[63:0] <- repl(flag)",
	"None", ORVDX64I,},
 
{"lv.any_le.h", "Vector Half-Word Elements Any Less or Equal Than",
	"All half-word elements of vector/floating-point register vfrA are compared "
	"to half-word elements of vector/floating-point register vfrB. Compare flag is "
	"set if any element of vfrA is less or equal than corresponding element of vfrB;"
	"otherwise compare flag is cleared. "
	"\\Compare flag is replicated into all bit positions of vector/floating-point "
	"register vfrD.",
	"",
	"flag <- vfrA[15:0] ,= vfrB[15:0] ||\\"
	"\tvfrA[31:16] <= vfrB[31:16] ||\\"
	"\tvfrA[47:32] <= vfrB[47:32] ||\\"
	"\tvfrA[63:48] <= vfrB[63:48]"
	"vfrD[63:0] <- repl(flag)",
	"None", ORVDX64I,},
 
{"lv.any_ne.b", "Vector Byte Elements Any Not Equal",
	"All byte elements of vector/floating-point register vfrA are compared "
	"to byte elements of vector/floating-point register vfrB. Compare flag is "
	"set if any two corresponding elements are not equal; otherwise compare flag is cleared. "
	"\\Compare flag is replicated into all bit positions of vector/floating-point "
	"register vfrD.",
	"",
	"flag <- vfrA[7:0] != vfrB[7:0] ||\\"
	"\tvfrA[15:8] != vfrB[15:8] ||\\"
	"\tvfrA[23:16] != vfrB[23:16] ||\\"
	"\tvfrA[31:24] != vfrB[31:24] ||\\"
	"\tvfrA[39:32] != vfrB[39:32] ||\\"
	"\tvfrA[47:40] != vfrB[47:40] ||\\"
	"\tvfrA[55:48] != vfrB[55:48] ||\\"
	"\tvfrA[63:56] != vfrB[63:56]"
	"vfrD[63:0] <- repl(flag)",
	"None", ORVDX64I,},
 
{"lv.any_ne.h", "Vector Half-Word Elements Any Not Equal",
	"All half-word elements of vector/floating-point register vfrA are compared "
	"to half-word elements of vector/floating-point register vfrB. Compare flag is "
	"set if any two corresponding elements are not equal; otherwise compare flag is cleared. "
	"\\Compare flag is replicated into all bit positions of vector/floating-point "
	"register vfrD.",
	"",
	"flag <- vfrA[15:0] != vfrB[15:0] ||\\"
	"\tvfrA[31:16] != vfrB[31:16] ||\\"
	"\tvfrA[47:32] != vfrB[47:32] ||\\"
	"\tvfrA[63:48] != vfrB[63:48]"
	"vfrD[63:0] <- repl(flag)",
	"None", ORVDX64I,},
 
{"lv.cmp_eq.b", "Vector Byte Elements Compare Equal",
	"All byte elements of vector/floating-point register vfrA are compared "
	"to byte elements of vector/floating-point register vfrB. Bits of the element "
	"in vector/floating-point register vfrD are set if two corresponding compared "
	"elements are equal; otherwise element bits are cleared. ",
	"",
	"vfrD[7:0] <- repl(vfrA[7:0] == vfrB[7:0]\\"
	"vfrD[15:8] <- repl(vfrA[15:8] == vfrB[15:8]\\"
	"vfrD[23:16] <- repl(vfrA[23:16] == vfrB[23:16]\\"
	"vfrD[31:24] <- repl(vfrA[31:24] == vfrB[31:24]\\"
	"vfrD[39:32] <- repl(vfrA[39:32] == vfrB[39:32]\\"
	"vfrD[47:40] <- repl(vfrA[47:40] == vfrB[47:40]\\"
	"vfrD[55:48] <- repl(vfrA[55:48] == vfrB[55:48]\\"
	"vfrD[63:56] <- repl(vfrA[63:56] == vfrB[63:56]\\",
	"None", ORVDX64I,},
 
{"lv.cmp_eq.h", "Vector Half-Word Elements Compare Equal",
	"All half-word elements of vector/floating-point register vfrA are compared "
	"to half-word elements of vector/floating-point register vfrB. Bits of the element "
	"in vector/floating-point register vfrD are set if two corresponding compared "
	"elements are equal; otherwise element bits are cleared. ",
	"",
	"vfrD[15:0] <- repl(vfrA[7:0] == vfrB[7:0]\\"
	"vfrD[31:16] <- repl(vfrA[23:16] == vfrB[23:16]\\"
	"vfrD[47:32] <- repl(vfrA[39:32] == vfrB[39:32]\\"
	"vfrD[63:48] <- repl(vfrA[55:48] == vfrB[55:48]\\",
	"None", ORVDX64I,},
 
{"lv.cmp_ge.b", "Vector Byte Elements Compare Greater Than or Equal",
	"All byte elements of vector/floating-point register vfrA are compared "
	"to byte elements of vector/floating-point register vfrB. Bits of the element "
	"in vector/floating-point register vfrD are set if element in vfrA is "
	"greater than or equal to element in vfrB; otherwise element bits are cleared. ",
	"",
	"vfrD[7:0] <- repl(vfrA[7:0] >= vfrB[7:0]\\"
	"vfrD[15:8] <- repl(vfrA[15:8] >= vfrB[15:8]\\"
	"vfrD[23:16] <- repl(vfrA[23:16] >= vfrB[23:16]\\"
	"vfrD[31:24] <- repl(vfrA[31:24] >= vfrB[31:24]\\"
	"vfrD[39:32] <- repl(vfrA[39:32] >= vfrB[39:32]\\"
	"vfrD[47:40] <- repl(vfrA[47:40] >= vfrB[47:40]\\"
	"vfrD[55:48] <- repl(vfrA[55:48] >= vfrB[55:48]\\"
	"vfrD[63:56] <- repl(vfrA[63:56] >= vfrB[63:56]\\",
	"None", ORVDX64I,},
 
{"lv.cmp_ge.h", "Vector Half-Word Elements Compare Greater Than or Equal",
	"All half-word elements of vector/floating-point register vfrA are compared "
	"to half-word elements of vector/floating-point register vfrB. Bits of the element "
	"in vector/floating-point register vfrD are set if element in vfrA is "
	"greater than or equal to element in vfrB; otherwise element bits are cleared. ",
	"",
	"vfrD[15:0] <- repl(vfrA[7:0] >= vfrB[7:0]\\"
	"vfrD[31:16] <- repl(vfrA[23:16] >= vfrB[23:16]\\"
	"vfrD[47:32] <- repl(vfrA[39:32] >= vfrB[39:32]\\"
	"vfrD[63:48] <- repl(vfrA[55:48] >= vfrB[55:48]\\",
	"None", ORVDX64I,},
 
{"lv.cmp_gt.b", "Vector Byte Elements Compare Greater Than",
	"All byte elements of vector/floating-point register vfrA are compared "
	"to byte elements of vector/floating-point register vfrB. Bits of the element "
	"in vector/floating-point register vfrD are set if element in vfrA is "
	"greater than element in vfrB; otherwise element bits are cleared. ",
	"",
	"vfrD[7:0] <- repl(vfrA[7:0] > vfrB[7:0]\\"
	"vfrD[15:8] <- repl(vfrA[15:8] > vfrB[15:8]\\"
	"vfrD[23:16] <- repl(vfrA[23:16] > vfrB[23:16]\\"
	"vfrD[31:24] <- repl(vfrA[31:24] > vfrB[31:24]\\"
	"vfrD[39:32] <- repl(vfrA[39:32] > vfrB[39:32]\\"
	"vfrD[47:40] <- repl(vfrA[47:40] > vfrB[47:40]\\"
	"vfrD[55:48] <- repl(vfrA[55:48] > vfrB[55:48]\\"
	"vfrD[63:56] <- repl(vfrA[63:56] > vfrB[63:56]\\",
	"None", ORVDX64I,},
 
{"lv.cmp_gt.h", "Vector Half-Word Elements Compare Greater Than",
	"All half-word elements of vector/floating-point register vfrA are compared "
	"to half-word elements of vector/floating-point register vfrB. Bits of the element "
	"in vector/floating-point register vfrD are set if element in vfrA is "
	"greater than element in vfrB; otherwise element bits are cleared. ",
	"",
	"vfrD[15:0] <- repl(vfrA[7:0] > vfrB[7:0]\\"
	"vfrD[31:16] <- repl(vfrA[23:16] > vfrB[23:16]\\"
	"vfrD[47:32] <- repl(vfrA[39:32] > vfrB[39:32]\\"
	"vfrD[63:48] <- repl(vfrA[55:48] > vfrB[55:48]\\",
	"None", ORVDX64I,},
 
{"lv.cmp_le.b", "Vector Byte Elements Compare Less Than or Equal",
	"All byte elements of vector/floating-point register vfrA are compared "
	"to byte elements of vector/floating-point register vfrB. Bits of the element "
	"in vector/floating-point register vfrD are set if element in vfrA is "
	"less than or equal to element in vfrB; otherwise element bits are cleared. ",
	"",
	"vfrD[7:0] <- repl(vfrA[7:0] <= vfrB[7:0]\\"
	"vfrD[15:8] <- repl(vfrA[15:8] <= vfrB[15:8]\\"
	"vfrD[23:16] <- repl(vfrA[23:16] <= vfrB[23:16]\\"
	"vfrD[31:24] <- repl(vfrA[31:24] <= vfrB[31:24]\\"
	"vfrD[39:32] <- repl(vfrA[39:32] <= vfrB[39:32]\\"
	"vfrD[47:40] <- repl(vfrA[47:40] <= vfrB[47:40]\\"
	"vfrD[55:48] <- repl(vfrA[55:48] <= vfrB[55:48]\\"
	"vfrD[63:56] <- repl(vfrA[63:56] <= vfrB[63:56]\\",
	"None", ORVDX64I,},
 
{"lv.cmp_le.h", "Vector Half-Word Elements Compare Less Than or Equal",
	"All half-word elements of vector/floating-point register vfrA are compared "
	"to half-word elements of vector/floating-point register vfrB. Bits of the element "
	"in vector/floating-point register vfrD are set if element in vfrA is "
	"less than or equal to element in vfrB; otherwise element bits are cleared. ",
	"",
	"vfrD[15:0] <- repl(vfrA[7:0] <= vfrB[7:0]\\"
	"vfrD[31:16] <- repl(vfrA[23:16] <= vfrB[23:16]\\"
	"vfrD[47:32] <- repl(vfrA[39:32] <= vfrB[39:32]\\"
	"vfrD[63:48] <- repl(vfrA[55:48] <= vfrB[55:48]\\",
	"None", ORVDX64I,},
 
{"lv.cmp_lt.b", "Vector Byte Elements Compare Less Than",
	"All byte elements of vector/floating-point register vfrA are compared "
	"to byte elements of vector/floating-point register vfrB. Bits of the element "
	"in vector/floating-point register vfrD are set if element in vfrA is "
	"less than element in vfrB; otherwise element bits are cleared. ",
	"",
	"vfrD[7:0] <- repl(vfrA[7:0] <= vfrB[7:0]\\"
	"vfrD[15:8] <- repl(vfrA[15:8] <= vfrB[15:8]\\"
	"vfrD[23:16] <- repl(vfrA[23:16] <= vfrB[23:16]\\"
	"vfrD[31:24] <- repl(vfrA[31:24] <= vfrB[31:24]\\"
	"vfrD[39:32] <- repl(vfrA[39:32] <= vfrB[39:32]\\"
	"vfrD[47:40] <- repl(vfrA[47:40] <= vfrB[47:40]\\"
	"vfrD[55:48] <- repl(vfrA[55:48] <= vfrB[55:48]\\"
	"vfrD[63:56] <- repl(vfrA[63:56] <= vfrB[63:56]\\",
	"None", ORVDX64I,},
 
{"lv.cmp_lt.h", "Vector Half-Word Elements Compare Less Than",
	"All half-word elements of vector/floating-point register vfrA are compared "
	"to half-word elements of vector/floating-point register vfrB. Bits of the element "
	"in vector/floating-point register vfrD are set if element in vfrA is "
	"less than element in vfrB; otherwise element bits are cleared. ",
	"",
	"vfrD[15:0] <- repl(vfrA[7:0] <= vfrB[7:0]\\"
	"vfrD[31:16] <- repl(vfrA[23:16] <= vfrB[23:16]\\"
	"vfrD[47:32] <- repl(vfrA[39:32] <= vfrB[39:32]\\"
	"vfrD[63:48] <- repl(vfrA[55:48] <= vfrB[55:48]\\",
	"None", ORVDX64I,},
 
{"lv.cmp_ne.b", "Vector Byte Elements Compare Not Equal",
	"All byte elements of vector/floating-point register vfrA are compared "
	"to byte elements of vector/floating-point register vfrB. Bits of the element "
	"in vector/floating-point register vfrD are set if two corresponding compared "
	"elements are not equal; otherwise element bits are cleared. ",
	"",
	"vfrD[7:0] <- repl(vfrA[7:0] != vfrB[7:0])\\"
	"vfrD[15:8] <- repl(vfrA[15:8] != vfrB[15:8])\\"
	"vfrD[23:16] <- repl(vfrA[23:16] != vfrB[23:16])\\"
	"vfrD[31:24] <- repl(vfrA[31:24] != vfrB[31:24])\\"
	"vfrD[39:32] <- repl(vfrA[39:32] != vfrB[39:32])\\"
	"vfrD[47:40] <- repl(vfrA[47:40] != vfrB[47:40])\\"
	"vfrD[55:48] <- repl(vfrA[55:48] != vfrB[55:48])\\"
	"vfrD[63:56] <- repl(vfrA[63:56] != vfrB[63:56])\\",
	"None", ORVDX64I,},
 
{"lv.cmp_ne.h", "Vector Half-Word Elements Compare Not Equal",
	"All half-word elements of vector/floating-point register vfrA are compared "
	"to half-word elements of vector/floating-point register vfrB. Bits of the element "
	"in vector/floating-point register vfrD are set if two corresponding compared "
	"elements are not equal; otherwise element bits are cleared. ",
	"",
	"vfrD[15:0] <- repl(vfrA[7:0] != vfrB[7:0])\\"
	"vfrD[31:16] <- repl(vfrA[23:16] != vfrB[23:16])\\"
	"vfrD[47:32] <- repl(vfrA[39:32] != vfrB[39:32])\\"
	"vfrD[63:48] <- repl(vfrA[55:48] != vfrB[55:48])\\",
	"None", ORVDX64I,},
 
{"lv.and", "Vector And",
	"The contents of vector/floating-point register vfrA are combined with the contents "
	"of vector/floating-point register vfrB in a bit-wise logical AND operation. The "
	"result is placed into vector/floating-point register vfrD.",
	"",
	"vfrD[63:0] <- vfrA[63:0] AND vfrB[63:0]",
	"None", ORVDX64I,},
 
{"lv.nand", "Vector Not And",
	"The contents of vector/floating-point register vfrA are combined with the contents "
	"of vector/floating-point register vfrB in a bit-wise logical NAND operation. The "
	"result is placed into vector/floating-point register vfrD.",
	"",
	"vfrD[63:0] <- vfrA[63:0] NAND vfrB[63:0]",
	"None", ORVDX64I,},
 
{"lv.nor", "Vector Not Or",
	"The contents of vector/floating-point register vfrA are combined with the contents "
	"of vector/floating-point register vfrB in a bit-wise logical NOR operation. The "
	"result is placed into vector/floating-point register vfrD.",
	"",
	"vfrD[63:0] <- vfrA[63:0] NOR vfrB[63:0]",
	"None", ORVDX64I,},
 
{"lv.or", "Vector Or",
	"The contents of vector/floating-point register vfrA are combined with the contents "
	"of vector/floating-point register vfrB in a bit-wise logical OR operation. The "
	"result is placed into vector/floating-point register vfrD.",
	"",
	"vfrD[63:0] <- vfrA[63:0] OR vfrB[63:0]",
	"None", ORVDX64I,},
 
{"lv.xor", "Vector Exclusive Or",
	"The contents of vector/floating-point register vfrA are combined with the contents "
	"of vector/floating-point register vfrB in a bit-wise logical XOR operation. The "
	"result is placed into vector/floating-point register vfrD.",
	"",
	"vfrD[63:0] <- vfrA[63:0] XOR vfrB[63:0]",
	"None", ORVDX64I,},
 
{"lv.add.b", "Vector Byte Elements Add Signed",
	"The byte elements of vector/floating-point register vfrA are added to the byte elements "
	"of vector/floating-point register vfrB to form the result elements. Result "
	"elements are placed into vector/floating-point register vfrD.",
	"",
	"vfrD[7:0] <- vfrA[7:0] + vfrB[7:0]\\"
	"vfrD[15:8] <- vfrA[15:8] + vfrB[15:8]\\"
	"vfrD[23:16] <- vfrA[23:16] + vfrB[23:16]\\"
	"vfrD[31:24] <- vfrA[31:24] + vfrB[31:24]\\"
	"vfrD[39:32] <- vfrA[39:32] + vfrB[39:32]\\"
	"vfrD[47:40] <- vfrA[47:40] + vfrB[47:40]\\"
	"vfrD[55:48] <- vfrA[55:48] + vfrB[55:48]\\"
	"vfrD[63:56] <- vfrA[63:56] + vfrB[63:56]",
	"None", ORVDX64I,},
 
{"lv.add.h", "Vector Half-Word Elements Add Signed",
	"The half-word elements of vector/floating-point register vfrA are added to the "
	"half-word elements of vector/floating-point register vfrB to form the result "
	"elements. Result elements are placed into vector/floating-point "
	"register vfrD.",
	"",
	"vfrD[15:0] <- vfrA[15:0] + vfrB[15:0]\\"
	"vfrD[31:16] <- vfrA[31:16] + vfrB[31:16]\\"
	"vfrD[47:32] <- vfrA[47:32] + vfrB[47:32]\\"
	"vfrD[63:48] <- vfrA[63:48] + vfrB[63:48]\\",
	"None", ORVDX64I,},
 
{"lv.sub.b", "Vector Byte Elements Subtract Signed",
	"The byte elements of vector/floating-point register vfrB are subtracted from the "
	"byte elements of vector/floating-point register vfrA to form the result elements. "
	"Result elements are placed into vector/floating-point register vfrD.",
	"",
	"vfrD[7:0] <- vfrA[7:0] - vfrB[7:0]\\"
	"vfrD[15:8] <- vfrA[15:8] - vfrB[15:8]\\"
	"vfrD[23:16] <- vfrA[23:16] - vfrB[23:16]\\"
	"vfrD[31:24] <- vfrA[31:24] - vfrB[31:24]\\"
	"vfrD[39:32] <- vfrA[39:32] - vfrB[39:32]\\"
	"vfrD[47:40] <- vfrA[47:40] - vfrB[47:40]\\"
	"vfrD[55:48] <- vfrA[55:48] - vfrB[55:48]\\"
	"vfrD[63:56] <- vfrA[63:56] - vfrB[63:56]",
	"None", ORVDX64I,},
 
{"lv.sub.h", "Vector Half-Word Elements Subtract Signed",
	"The half-word elements of vector/floating-point register vfrB are subtracted from the "
	"half-word elements of vector/floating-point register vfrA to form the result "
	"elements. Result elements are placed into vector/floating-point "
	"register vfrD.",
	"",
	"vfrD[15:0] <- vfrA[15:0] - vfrB[15:0]\\"
	"vfrD[31:16] <- vfrA[31:16] - vfrB[31:16]\\"
	"vfrD[47:32] <- vfrA[47:32] - vfrB[47:32]\\"
	"vfrD[63:48] <- vfrA[63:48] - vfrB[63:48]\\",
	"None", ORVDX64I,},
 
{"lv.adds.b", "Vector Byte Elements Add Signed Saturated",
	"The byte elements of vector/floating-point register vfrA are added to the byte elements "
	"of vector/floating-point register vfrB to form the result elements. If the result "
	" exceeds min/max value for the destination data type, it is saturated to min/max value "
	" and placed into vector/floating-point register vfrD.",
	"",
	"vfrD[7:0] <- sat8s(vfrA[7:0] + vfrB[7:0])\\"
	"vfrD[15:8] <- sat8s(vfrA[15:8] + vfrB[15:8])\\"
	"vfrD[23:16] <- sat8s(vfrA[23:16] + vfrB[23:16])\\"
	"vfrD[31:24] <- sat8s(vfrA[31:24] + vfrB[31:24])\\"
	"vfrD[39:32] <- sat8s(vfrA[39:32] + vfrB[39:32])\\"
	"vfrD[47:40] <- sat8s(vfrA[47:40] + vfrB[47:40])\\"
	"vfrD[55:48] <- sat8s(vfrA[55:48] + vfrB[55:48])\\"
	"vfrD[63:56] <- sat8s(vfrA[63:56] + vfrB[63:56])",
	"None", ORVDX64I,},
 
{"lv.adds.h", "Vector Half-Word Elements Add Signed Saturated",
	"The half-word elements of vector/floating-point register vfrA are added to the "
	"half-word elements of vector/floating-point register vfrB to form the result "
	"elements. If the result exceeds min/max value for the destination data type, "
	"it is saturated to min/max value and placed into vector/floating-point register vfrD.",
	"",
	"vfrD[15:0] <- sat16s(vfrA[15:0] + vfrB[15:0])\\"
	"vfrD[31:16] <- sat16s(vfrA[31:16] + vfrB[31:16])\\"
	"vfrD[47:32] <- sat16s(vfrA[47:32] + vfrB[47:32])\\"
	"vfrD[63:48] <- sat16s(vfrA[63:48] + vfrB[63:48])",
	"None", ORVDX64I,},
 
{"lv.subs.b", "Vector Byte Elements Subtract Signed Saturated",
	"The byte elements of vector/floating-point register vfrB are subtracted from the byte elements "
	"of vector/floating-point register vfrA to form the result elements. If the result "
	"exceeds min/max value for the destination data type, it is saturated to min/max value "
	"and placed into vector/floating-point register vfrD.",
	"",
	"vfrD[7:0] <- sat8s(vfrA[7:0] + vfrB[7:0])\\"
	"vfrD[15:8] <- sat8s(vfrA[15:8] + vfrB[15:8])\\"
	"vfrD[23:16] <- sat8s(vfrA[23:16] + vfrB[23:16])\\"
	"vfrD[31:24] <- sat8s(vfrA[31:24] + vfrB[31:24])\\"
	"vfrD[39:32] <- sat8s(vfrA[39:32] + vfrB[39:32])\\"
	"vfrD[47:40] <- sat8s(vfrA[47:40] + vfrB[47:40])\\"
	"vfrD[55:48] <- sat8s(vfrA[55:48] + vfrB[55:48])\\"
	"vfrD[63:56] <- sat8s(vfrA[63:56] + vfrB[63:56])",
	"None", ORVDX64I,},
 
{"lv.subs.h", "Vector Half-Word Elements Subtract Signed Saturated",
	"The half-word elements of vector/floating-point register vfrB are subtracted from the "
	"half-word elements of vector/floating-point register vfrA to form the result "
	"elements. If the result exceeds min/max value for the destination data type, "
	"it is saturated to min/max value and placed into vector/floating-point register vfrD.",
	"",
	"vfrD[15:0] <- sat16s(vfrA[15:0] - vfrB[15:0])\\"
	"vfrD[31:16] <- sat16s(vfrA[31:16] - vfrB[31:16])\\"
	"vfrD[47:32] <- sat16s(vfrA[47:32] - vfrB[47:32])\\"
	"vfrD[63:48] <- sat16s(vfrA[63:48] - vfrB[63:48])",
	"None", ORVDX64I,},
 
{"lv.addu.b", "Vector Byte Elements Add Unsigned",
	"The unsigned byte elements of vector/floating-point register vfrA are added to "
	"the unsigned byte elements of vector/floating-point register vfrB to form the "
	"result elements. Result elements are placed into vector/floating-point register vfrD.",
	"",
	"vfrD[7:0] <- vfrA[7:0] + vfrB[7:0]\\"
	"vfrD[15:8] <- vfrA[15:8] + vfrB[15:8]\\"
	"vfrD[23:16] <- vfrA[23:16] + vfrB[23:16]\\"
	"vfrD[31:24] <- vfrA[31:24] + vfrB[31:24]\\"
	"vfrD[39:32] <- vfrA[39:32] + vfrB[39:32]\\"
	"vfrD[47:40] <- vfrA[47:40] + vfrB[47:40]\\"
	"vfrD[55:48] <- vfrA[55:48] + vfrB[55:48]\\"
	"vfrD[63:56] <- vfrA[63:56] + vfrB[63:56]",
	"None", ORVDX64I,},
 
{"lv.addu.h", "Vector Half-Word Elements Add Unsigned",
	"The unsigned half-word elements of vector/floating-point register vfrA are added to the "
	"unsigned half-word elements of vector/floating-point register vfrB to form the result "
	"elements. Result elements are placed into vector/floating-point "
	"register vfrD.",
	"",
	"vfrD[15:0] <- vfrA[15:0] + vfrB[15:0]\\"
	"vfrD[31:16] <- vfrA[31:16] + vfrB[31:16]\\"
	"vfrD[47:32] <- vfrA[47:32] + vfrB[47:32]\\"
	"vfrD[63:48] <- vfrA[63:48] + vfrB[63:48]\\",
	"None", ORVDX64I,},
 
{"lv.subu.b", "Vector Byte Elements Subtract Unsigned",
	"The unsigned byte elements of vector/floating-point register vfrB are subtracted from the "
	"unsigned byte elements of vector/floating-point register vfrA to form the result elements. "
	"Result elements are placed into vector/floating-point register vfrD.",
	"",
	"vfrD[7:0] <- vfrA[7:0] - vfrB[7:0]\\"
	"vfrD[15:8] <- vfrA[15:8] - vfrB[15:8]\\"
	"vfrD[23:16] <- vfrA[23:16] - vfrB[23:16]\\"
	"vfrD[31:24] <- vfrA[31:24] - vfrB[31:24]\\"
	"vfrD[39:32] <- vfrA[39:32] - vfrB[39:32]\\"
	"vfrD[47:40] <- vfrA[47:40] - vfrB[47:40]\\"
	"vfrD[55:48] <- vfrA[55:48] - vfrB[55:48]\\"
	"vfrD[63:56] <- vfrA[63:56] - vfrB[63:56]",
	"None", ORVDX64I,},
 
{"lv.subu.h", "Vector Half-Word Elements Subtract Unsigned",
	"The unsigned half-word elements of vector/floating-point register vfrB are subtracted from the "
	"unsigned half-word elements of vector/floating-point register vfrA to form the result "
	"elements. Result elements are placed into vector/floating-point "
	"register vfrD.",
	"",
	"vfrD[15:0] <- vfrA[15:0] - vfrB[15:0]\\"
	"vfrD[31:16] <- vfrA[31:16] - vfrB[31:16]\\"
	"vfrD[47:32] <- vfrA[47:32] - vfrB[47:32]\\"
	"vfrD[63:48] <- vfrA[63:48] - vfrB[63:48]\\",
	"None", ORVDX64I,},
 
{"lv.addus.b", "Vector Byte Elements Add Unsigned Saturated",
	"The unsigned byte elements of vector/floating-point register vfrA are added to the "
	"unsigned byte elements of vector/floating-point register vfrB to form the result "
	"elements. If the result exceeds min/max value for the destination data type, "
	"it is saturated to min/max value and placed into vector/floating-point register vfrD.",
	"",
	"vfrD[7:0] <- sat8u(vfrA[7:0] + vfrB[7:0])\\"
	"vfrD[15:8] <- sat8u(vfrA[15:8] + vfrB[15:8])\\"
	"vfrD[23:16] <- sat8u(vfrA[23:16] + vfrB[23:16])\\"
	"vfrD[31:24] <- sat8u(vfrA[31:24] + vfrB[31:24])\\"
	"vfrD[39:32] <- sat8u(vfrA[39:32] + vfrB[39:32])\\"
	"vfrD[47:40] <- sat8u(vfrA[47:40] + vfrB[47:40])\\"
	"vfrD[55:48] <- sat8u(vfrA[55:48] + vfrB[55:48])\\"
	"vfrD[63:56] <- sat8u(vfrA[63:56] + vfrB[63:56])",
	"None", ORVDX64I,},
 
{"lv.addus.h", "Vector Half-Word Elements Add Unsigned Saturated",
	"The unsigned half-word elements of vector/floating-point register vfrA are added to the "
	"unsigned half-word elements of vector/floating-point register vfrB to form the result "
	"elements. If the result exceeds min/max value for the destination data type, "
	"it is saturated to min/max value and placed into vector/floating-point register vfrD.",
	"",
	"vfrD[15:0] <- sat16s(vfrA[15:0] + vfrB[15:0])\\"
	"vfrD[31:16] <- sat16s(vfrA[31:16] + vfrB[31:16])\\"
	"vfrD[47:32] <- sat16s(vfrA[47:32] + vfrB[47:32])\\"
	"vfrD[63:48] <- sat16s(vfrA[63:48] + vfrB[63:48])",
	"None", ORVDX64I,},
 
{"lv.subus.b", "Vector Byte Elements Subtract Unsigned Saturated",
	"The unsigned byte elements of vector/floating-point register vfrB are subtracted from "
	"the unsigned byte elements of vector/floating-point register vfrA to form the result "
	"elements. If the result exceeds min/max value for the destination data type, it is "
	"saturated to min/max value and placed into vector/floating-point register vfrD.",
	"",
	"vfrD[7:0] <- sat8u(vfrA[7:0] + vfrB[7:0])\\"
	"vfrD[15:8] <- sat8u(vfrA[15:8] + vfrB[15:8])\\"
	"vfrD[23:16] <- sat8u(vfrA[23:16] + vfrB[23:16])\\"
	"vfrD[31:24] <- sat8u(vfrA[31:24] + vfrB[31:24])\\"
	"vfrD[39:32] <- sat8u(vfrA[39:32] + vfrB[39:32])\\"
	"vfrD[47:40] <- sat8u(vfrA[47:40] + vfrB[47:40])\\"
	"vfrD[55:48] <- sat8u(vfrA[55:48] + vfrB[55:48])\\"
	"vfrD[63:56] <- sat8u(vfrA[63:56] + vfrB[63:56])",
	"None", ORVDX64I,},
 
{"lv.subus.h", "Vector Half-Word Elements Subtract Unsigned Saturated",
	"The unsigned half-word elements of vector/floating-point register vfrB are subtracted "
	"from the unsigned half-word elements of vector/floating-point register vfrA to form "
	"the result elements. If the result exceeds min/max value for the destination data type, "
	"it is saturated to min/max value and placed into vector/floating-point register vfrD.",
	"",
	"vfrD[15:0] <- sat16u(vfrA[15:0] - vfrB[15:0])\\"
	"vfrD[31:16] <- sat16u(vfrA[31:16] - vfrB[31:16])\\"
	"vfrD[47:32] <- sat16u(vfrA[47:32] - vfrB[47:32])\\"
	"vfrD[63:48] <- sat16u(vfrA[63:48] - vfrB[63:48])",
	"None", ORVDX64I,},
 
{"lv.avg.b", "Vector Byte Elements Average",
	"The byte elements of vector/floating-point register vfrA are added to the byte elements "
	"of vector/floating-point register vfrB and the sum is shifted right by one to form the "
	"result elements. Result elements are placed into vector/floating-point register vfrD.",
	"",
	"vfrD[7:0] <- (vfrA[7:0] + vfrB[7:0]) >> 1\\"
	"vfrD[15:8] <- (vfrA[15:8] + vfrB[15:8]) >> 1\\"
	"vfrD[23:16] <- (vfrA[23:16] + vfrB[23:16]) >> 1\\"
	"vfrD[31:24] <- (vfrA[31:24] + vfrB[31:24]) >> 1\\"
	"vfrD[39:32] <- (vfrA[39:32] + vfrB[39:32]) >> 1\\"
	"vfrD[47:40] <- (vfrA[47:40] + vfrB[47:40]) >> 1\\"
	"vfrD[55:48] <- (vfrA[55:48] + vfrB[55:48]) >> 1\\"
	"vfrD[63:56] <- (vfrA[63:56] + vfrB[63:56]) >> 1",
	"None", ORVDX64I,},
 
{"lv.avg.h", "Vector Half-Word Elements Average",
	"The half-word elements of vector/floating-point register vfrA are added to the "
	"half-word elements of vector/floating-point register vfrB and the sum is shifted "
	"right by one to form the result elements. Result elements are placed into "
	"vector/floating-point register vfrD.",
	"",
	"vfrD[15:0] <- (vfrA[15:0] + vfrB[15:0]) >> 1\\"
	"vfrD[31:16] <- (vfrA[31:16] + vfrB[31:16]) >> 1\\"
	"vfrD[47:32] <- (vfrA[47:32] + vfrB[47:32]) >> 1\\"
	"vfrD[63:48] <- (vfrA[63:48] + vfrB[63:48]) >> 1\\",
	"None", ORVDX64I,},
 
{"lv.max.b", "Vector Byte Elements Maximum",
	"The byte elements of vector/floating-point register vfrA are compared to the byte elements "
	"of vector/floating-point register vfrB and larger elements are selected to form the "
	"result elements. Result elements are placed into vector/floating-point register vfrD.",
	"",
	"vfrD[7:0] <- vfrA[7:0] > vfrB[7:0] ? vfrA[7:0] : vrfB[7:0]\\"
	"vfrD[15:8] <- vfrA[15:8] > vfrB[15:8] ? vfrA[15:8] : vrfB[15:8]\\"
	"vfrD[23:16] <- vfrA[23:16] > vfrB[23:16] ? vfrA[23:16] : vrfB[23:16]\\"
	"vfrD[31:24] <- vfrA[31:24] > vfrB[31:24] ? vfrA[31:24] : vrfB[31:24]\\"
	"vfrD[39:32] <- vfrA[39:32] > vfrB[39:32] ? vfrA[39:32] : vrfB[39:32]\\"
	"vfrD[47:40] <- vfrA[47:40] > vfrB[47:40] ? vfrA[47:40] : vrfB[47:40]\\"
	"vfrD[55:48] <- vfrA[55:48] > vfrB[55:48] ? vfrA[55:48] : vrfB[55:48]\\"
	"vfrD[63:56] <- vfrA[63:56] > vfrB[63:56] ? vfrA[63:56] : vrfB[63:56]",
	"None", ORVDX64I,},
 
{"lv.max.h", "Vector Half-Word Elements Maximum",
	"The half-word elements of vector/floating-point register vfrA are compared to the "
	"half-word elements of vector/floating-point register vfrB and larger elements "
	"are selected to form the result elements. Result elements are placed into "
	"vector/floating-point register vfrD.",
	"",
	"vfrD[15:0] <- vfrA[15:0] > vfrB[15:0] ? vfrA[15:0] : vrfB[15:0]\\"
	"vfrD[31:16] <- vfrA[31:16] > vfrB[31:16] ? vfrA[31:16] : vrfB[31:16]\\"
	"vfrD[47:32] <- vfrA[47:32] > vfrB[47:32] ? vfrA[47:32] : vrfB[47:32]\\"
	"vfrD[63:48] <- vfrA[63:48] > vfrB[63:48] ? vfrA[63:48] : vrfB[63:48]\\",
	"None", ORVDX64I,},
 
{"lv.min.b", "Vector Byte Elements Minimum",
	"The byte elements of vector/floating-point register vfrA are compared to the byte elements "
	"of vector/floating-point register vfrB and smaller elements are selected to form the "
	"result elements. Result elements are placed into vector/floating-point register vfrD.",
	"",
	"vfrD[7:0] <- vfrA[7:0] < vfrB[7:0] ? vfrA[7:0] : vrfB[7:0]\\"
	"vfrD[15:8] <- vfrA[15:8] < vfrB[15:8] ? vfrA[15:8] : vrfB[15:8]\\"
	"vfrD[23:16] <- vfrA[23:16] < vfrB[23:16] ? vfrA[23:16] : vrfB[23:16]\\"
	"vfrD[31:24] <- vfrA[31:24] < vfrB[31:24] ? vfrA[31:24] : vrfB[31:24]\\"
	"vfrD[39:32] <- vfrA[39:32] < vfrB[39:32] ? vfrA[39:32] : vrfB[39:32]\\"
	"vfrD[47:40] <- vfrA[47:40] < vfrB[47:40] ? vfrA[47:40] : vrfB[47:40]\\"
	"vfrD[55:48] <- vfrA[55:48] < vfrB[55:48] ? vfrA[55:48] : vrfB[55:48]\\"
	"vfrD[63:56] <- vfrA[63:56] < vfrB[63:56] ? vfrA[63:56] : vrfB[63:56]",
	"None", ORVDX64I,},
 
{"lv.min.h", "Vector Half-Word Elements Minimum",
	"The half-word elements of vector/floating-point register vfrA are compared to the "
	"half-word elements of vector/floating-point register vfrB and smaller elements "
	"are selected to form the result elements. Result elements are placed into "
	"vector/floating-point register vfrD.",
	"",
	"vfrD[15:0] <- vfrA[15:0] < vfrB[15:0] ? vfrA[15:0] : vrfB[15:0]\\"
	"vfrD[31:16] <- vfrA[31:16] < vfrB[31:16] ? vfrA[31:16] : vrfB[31:16]\\"
	"vfrD[47:32] <- vfrA[47:32] < vfrB[47:32] ? vfrA[47:32] : vrfB[47:32]\\"
	"vfrD[63:48] <- vfrA[63:48] < vfrB[63:48] ? vfrA[63:48] : vrfB[63:48]\\",
	"None", ORVDX64I,},
 
{"lv.sll.b", "Vector Byte Elements Shift Left Logical",
	"The contents of byte elements of vector/floating-point register vfrA are "
	"shifted left by the number of bits specified in lower 3 bits in each byte element "
	"of vector/floating-point register vfrB, inserting zeros into the low-order bits "
	"elements. Result elements are placed into vector/floating-point register vfrD.",
	"",
	"vfrD[7:0] <- vfrA[7:0] << vfrB[2:0]\\"
	"vfrD[15:8] <- vfrA[15:8] << vfrB[10:8]\\"
	"vfrD[23:16] <- vfrA[23:16] << vfrB[18:16]\\"
	"vfrD[31:24] <- vfrA[31:24] << vfrB[26:24]\\"
	"vfrD[39:32] <- vfrA[39:32] << vfrB[34:32]\\"
	"vfrD[47:40] <- vfrA[47:40] << vfrB[42:40]\\"
	"vfrD[55:48] <- vfrA[55:48] << vfrB[50:48]\\"
	"vfrD[63:56] <- vfrA[63:56] << vfrB[58:56]",
	"None", ORVDX64I,},
 
{"lv.sll.h", "Vector Half-Word Elements Shift Left Logical",
	"The contents of half-word elements of vector/floating-point register vfrA are "
	"shifted left by the number of bits specified in lower 4 bits in each half-word element "
	"of vector/floating-point register vfrB, inserting zeros into the low-order bits "
	"elements. Result elements are placed into vector/floating-point register vfrD.",
	"",
	"vfrD[15:0] <- vfrA[15:0] << vfrB[3:0]\\"
	"vfrD[31:16] <- vfrA[31:16] << vfrB[19:16]\\"
	"vfrD[47:32] <- vfrA[47:32] << vfrB[35:32]\\"
	"vfrD[63:48] <- vfrA[63:48] << vfrB[51:48]\\",
	"None", ORVDX64I,},
 
{"lv.srl.b", "Vector Byte Elements Shift Right Logical",
	"The contents of byte elements of vector/floating-point register vfrA are "
	"shifted right by the number of bits specified in lower 3 bits in each byte element "
	"of vector/floating-point register vfrB, inserting zeros into the high-order bits "
	"elements. Result elements are placed into vector/floating-point register vfrD.",
	"",
	"vfrD[7:0] <- vfrA[7:0] >> vfrB[2:0]\\"
	"vfrD[15:8] <- vfrA[15:8] >> vfrB[10:8]\\"
	"vfrD[23:16] <- vfrA[23:16] >> vfrB[18:16]\\"
	"vfrD[31:24] <- vfrA[31:24] >> vfrB[26:24]\\"
	"vfrD[39:32] <- vfrA[39:32] >> vfrB[34:32]\\"
	"vfrD[47:40] <- vfrA[47:40] >> vfrB[42:40]\\"
	"vfrD[55:48] <- vfrA[55:48] >> vfrB[50:48]\\"
	"vfrD[63:56] <- vfrA[63:56] >> vfrB[58:56]",
	"None", ORVDX64I,},
 
{"lv.srl.h", "Vector Half-Word Elements Shift Right Logical",
	"The contents of half-word elements of vector/floating-point register vfrA are "
	"shifted right by the number of bits specified in lower 4 bits in each half-word element "
	"of vector/floating-point register vfrB, inserting zeros into the low-order bits of "
	"elements. Result elements are placed into vector/floating-point register vfrD.",
	"",
	"vfrD[15:0] <- vfrA[15:0] >> vfrB[3:0]\\"
	"vfrD[31:16] <- vfrA[31:16] >> vfrB[19:16]\\"
	"vfrD[47:32] <- vfrA[47:32] >> vfrB[35:32]\\"
	"vfrD[63:48] <- vfrA[63:48] >> vfrB[51:48]\\",
	"None", ORVDX64I,},
 
{"lv.sra.b", "Vector Byte Elements Shift Right Arithmetic",
	"The contents of byte elements of vector/floating-point register vfrA are "
	"shifted right by the number of bits specified in lower 3 bits in each byte element "
	"of vector/floating-point register vfrB, inserting most significat bit of each "
	"element into the high-order bits. "
	"Result elements are placed into vector/floating-point register vfrD.",
	"",
	"vfrD[7:0] <- vfrA[7:0] sra vfrB[2:0]\\"
	"vfrD[15:8] <- vfrA[15:8] sra vfrB[10:8]\\"
	"vfrD[23:16] <- vfrA[23:16] sra vfrB[18:16]\\"
	"vfrD[31:24] <- vfrA[31:24] sra vfrB[26:24]\\"
	"vfrD[39:32] <- vfrA[39:32] sra vfrB[34:32]\\"
	"vfrD[47:40] <- vfrA[47:40] sra vfrB[42:40]\\"
	"vfrD[55:48] <- vfrA[55:48] sra vfrB[50:48]\\"
	"vfrD[63:56] <- vfrA[63:56] sra vfrB[58:56]",
	"None", ORVDX64I,},
 
{"lv.sra.h", "Vector Half-Word Elements Shift Right Arithmetic",
	"The contents of half-word elements of vector/floating-point register vfrA are "
	"shifted right by the number of bits specified in lower 4 bits in each half-word element "
	"of vector/floating-point register vfrB, inserting most significant bit of each element "
	"into the low-order bits. "
	"Result elements are placed into vector/floating-point register vfrD.",
	"",
	"vfrD[15:0] <- vfrA[15:0] sra vfrB[3:0]\\"
	"vfrD[31:16] <- vfrA[31:16] sra vfrB[19:16]\\"
	"vfrD[47:32] <- vfrA[47:32] sra vfrB[35:32]\\"
	"vfrD[63:48] <- vfrA[63:48] sra vfrB[51:48]\\",
	"None", ORVDX64I,},
 
{"lv.rl.b", "Vector Byte Elements Rotate Left",
	"The contents of byte elements of vector/floating-point register vfrA are "
	"rotated left by the number of bits specified in lower 3 bits in each byte element "
	"of vector/floating-point register vfrB. "
	"Result elements are placed into vector/floating-point register vfrD.",
	"",
	"vfrD[7:0] <- vfrA[7:0] rl vfrB[2:0]\\"
	"vfrD[15:8] <- vfrA[15:8] rl vfrB[10:8]\\"
	"vfrD[23:16] <- vfrA[23:16] rl vfrB[18:16]\\"
	"vfrD[31:24] <- vfrA[31:24] rl vfrB[26:24]\\"
	"vfrD[39:32] <- vfrA[39:32] rl vfrB[34:32]\\"
	"vfrD[47:40] <- vfrA[47:40] rl vfrB[42:40]\\"
	"vfrD[55:48] <- vfrA[55:48] rl vfrB[50:48]\\"
	"vfrD[63:56] <- vfrA[63:56] rl vfrB[58:56]",
	"None", ORVDX64I,},
 
{"lv.rl.h", "Vector Half-Word Elements Rotate Left",
	"The contents of half-word elements of vector/floating-point register vfrA are "
	"rotated left by the number of bits specified in lower 4 bits in each half-word element "
	"of vector/floating-point register vfrB. "
	"Result elements are placed into vector/floating-point register vfrD.",
	"",
	"vfrD[15:0] <- vfrA[15:0] rl vfrB[3:0]\\"
	"vfrD[31:16] <- vfrA[31:16] rl vfrB[19:16]\\"
	"vfrD[47:32] <- vfrA[47:32] rl vfrB[35:32]\\"
	"vfrD[63:48] <- vfrA[63:48] rl vfrB[51:48]\\",
	"None", ORVDX64I,},
 
{"lv.sll", "Vector Shift Left Logical",
	"The contents of vector/floating-point register vfrA are "
	"shifted left by the number of bits specified in lower 4 bits in each byte element "
	"of vector/floating-point register vfrB, inserting zeros into the low-order bits of "
	"vfrD. "
	"Result elements are placed into vector/floating-point register vfrD.",
	"",
	"vfrD[63:0] <- vfrA[63:0] << vfrB[2:0]",
	"None", ORVDX64I,},
 
{"lv.srl", "Vector Shift Right Logical",
	"The contents of vector/floating-point register vfrA are "
	"shifted right by the number of bits specified in lower 4 bits in each byte element "
	"of vector/floating-point register vfrB, inserting zeros into the high-order bits of "
	"vfrD. "
	"Result elements are placed into vector/floating-point register vfrD.",
	"",
	"vfrD[63:0] <- vfrA[63:0] >> vfrB[2:0]",
	"None", ORVDX64I,},
 
{"lv.merge.b", "Vector Byte Elements Merge",
	"Byte elements of the lower half of the vector/floating-point register vfrA are "
	"combined with the byte elements of the lower half of vector/floating-point "
	"register vfrB in such a way that lowest element is from the vfrB, second element "
	"from the vfrA, third again from the vfrB etc. "
	"Result elements are placed into vector/floating-point register vfrD.",
	"",
	"vfrD[7:0] <- vfrB[7:0]\\"
	"vfrD[15:8] <- vfrA[15:8]\\"
	"vfrD[23:16] <- vfrB[23:16]\\"
	"vfrD[31:24] <- vfrA[31:24]\\"
	"vfrD[39:32] <- vfrB[39:32]\\"
	"vfrD[47:40] <- vfrA[47:40]\\"
	"vfrD[55:48] <- vfrB[55:48]\\"
	"vfrD[63:56] <- vfrA[63:56]",
	"None", ORVDX64I,},
 
{"lv.merge.h", "Vector Half-Word Elements Merge",
	"Half-word elements of the lower half of the vector/floating-point register vfrA are "
	"combined with the byte elements of the lower half of vector/floating-point "
	"register vfrB in such a way that lowest element is from the vfrB, second element "
	"from the vfrA, third again from the vfrB etc. "
	"Result elements are placed into vector/floating-point register vfrD.",
	"",
	"vfrD[15:0] <- vfrB[15:0]\\"
	"vfrD[31:16] <- vfrA[31:16]\\"
	"vfrD[47:32] <- vfrB[47:32]\\"
	"vfrD[63:48] <- vfrA[63:48]",
	"None", ORVDX64I,},
 
{"lv.pack.b", "Vector Byte Elements Pack",
	"Lower half of the byte elements of the vector/floating-point register vfrA are "
	"truncated and combined with the lower half of the byte truncated elements of the "
	"vector/floating-point register vfrB in such a way that lowest elements are from "
	"vfrB and highest element from vfrA. "
	"Result elements are placed into vector/floating-point register vfrD.",
	"",
	"vfrD[3:0] <- vfrB[3:0]\\"
	"vfrD[7:4] <- vfrB[11:8]\\"
	"vfrD[11:8] <- vfrB[19:16]\\"
	"vfrD[15:12] <- vfrB[27:24]\\"
	"vfrD[19:16] <- vfrB[35:32]\\"
	"vfrD[23:20] <- vfrB[43:40]\\"
	"vfrD[27:24] <- vfrB[51:48]\\"
	"vfrD[31:28] <- vfrB[59:56]\\"
	"vfrD[35:32] <- vfrA[3:0]\\"
	"vfrD[39:36] <- vfrA[11:8]\\"
	"vfrD[43:40] <- vfrA[19:16]\\"
	"vfrD[47:44] <- vfrA[27:24]\\"
	"vfrD[51:48] <- vfrA[35:32]\\"
	"vfrD[55:52] <- vfrA[43:40]\\"
	"vfrD[59:56] <- vfrA[51:48]\\"
	"vfrD[63:60] <- vfrA[59:56]",
	"None", ORVDX64I,},
 
{"lv.pack.h", "Vector Half-word Elements Pack",
	"Lower half of the half-word elements of the vector/floating-point register vfrA are "
	"truncated and combined with the lower half of the half-word truncated elements of the "
	"vector/floating-point register vfrB in such a way that lowest elements are from vfrB and highest element "
	"from vfrA. "
	"Result elements are placed into vector/floating-point register vfrD.",
	"",
	"vfrD[7:0] <- vfrB[15:0]\\"
	"vfrD[15:8] <- vfrB[31:16]\\"
	"vfrD[23:16] <- vfrB[47:32]\\"
	"vfrD[31:24] <- vfrB[63:48]\\"
	"vfrD[39:32] <- vfrA[15:0]\\"
	"vfrD[47:40] <- vfrA[31:16]\\"
	"vfrD[55:48] <- vfrA[47:32]\\"
	"vfrD[63:56] <- vfrA[63:48]\\",
	"None", ORVDX64I,},
 
{"lv.packs.b", "Vector Byte Elements Pack Signed Saturated",
	"Lower half of the signed byte elements of the vector/floating-point register vfrA are "
	"truncated and combined with the lower half of the signed byte truncated elements of "
	"the vector/floating-point register vfrB in such a way that lowest elements are from "
	"vfrB and highest element from vfrA. "
	"If any truncated element exceeds signed 4-bit value, it is saturated. "
	"Result elements are placed into vector/floating-point register vfrD.",
	"",
	"vfrD[3:0] <- sat4s(vfrB[7:0]\\"
	"vfrD[7:4] <- sat4s(vfrB[15:8]\\"
	"vfrD[11:8] <- sat4s(vfrB[23:16]\\"
	"vfrD[15:12] <- sat4s(vfrB[31:24]\\"
	"vfrD[19:16] <- sat4s(vfrB[39:32]\\"
	"vfrD[23:20] <- sat4s(vfrB[47:40]\\"
	"vfrD[27:24] <- sat4s(vfrB[55:48]\\"
	"vfrD[31:28] <- sat4s(vfrB[63:56]\\"
	"vfrD[35:32] <- sat4s(vfrA[7:0]\\"
	"vfrD[39:36] <- sat4s(vfrA[15:8]\\"
	"vfrD[43:40] <- sat4s(vfrA[23:16]\\"
	"vfrD[47:44] <- sat4s(vfrA[31:24]\\"
	"vfrD[51:48] <- sat4s(vfrA[39:32]\\"
	"vfrD[55:52] <- sat4s(vfrA[47:40]\\"
	"vfrD[59:56] <- sat4s(vfrA[55:48]\\"
	"vfrD[63:60] <- sat4s(vfrA[63:56]",
	"None", ORVDX64I,},
 
{"lv.packs.h", "Vector Half-word Elements Pack Signed Saturated",
	"Lower half of the signed halfpword elements of the vector/floating-point register "
	"vfrA are truncated and combined with the lower half of the signed half-word "
	"truncated elements of the vector/floating-point register vfrB in such a way "
	"that lowest elements are from vfrB and highest element from vfrA. "
	"If any truncated element exceeds signed 8-bit value, it is saturated. "
	"Result elements are placed into vector/floating-point register vfrD.",
	"",
	"vfrD[7:0] <- sat8s(vfrB[15:0])\\"
	"vfrD[15:8] <- sat8s(vfrB[31:16])\\"
	"vfrD[23:16] <- sat8s(vfrB[47:32])\\"
	"vfrD[31:24] <- sat8s(vfrB[63:48])\\"
	"vfrD[39:32] <- sat8s(vfrA[15:0])\\"
	"vfrD[47:40] <- sat8s(vfrA[31:16])\\"
	"vfrD[55:48] <- sat8s(vfrA[47:32])\\"
	"vfrD[63:56] <- sat8s(vfrA[63:48])\\",
	"None", ORVDX64I,},
 
{"lv.packus.b", "Vector Byte Elements Pack Unsigned Saturated",
	"Lower half of the unsigned byte elements of the vector/floating-point register vfrA are "
	"truncated and combined with the lower half of the unsigned byte truncated elements of "
	"the vector/floating-point register vfrB in such a way that lowest elements are from "
	"vfrB and highest element from vfrA. "
	"If any truncated element exceeds unsigned 4-bit value, it is saturated. "
	"Result elements are placed into vector/floating-point register vfrD.",
	"",
	"vfrD[3:0] <- sat4u(vfrB[7:0]\\"
	"vfrD[7:4] <- sat4u(vfrB[15:8]\\"
	"vfrD[11:8] <- sat4u(vfrB[23:16]\\"
	"vfrD[15:12] <- sat4u(vfrB[31:24]\\"
	"vfrD[19:16] <- sat4u(vfrB[39:32]\\"
	"vfrD[23:20] <- sat4u(vfrB[47:40]\\"
	"vfrD[27:24] <- sat4u(vfrB[55:48]\\"
	"vfrD[31:28] <- sat4u(vfrB[63:56]\\"
	"vfrD[35:32] <- sat4u(vfrA[7:0]\\"
	"vfrD[39:36] <- sat4u(vfrA[15:8]\\"
	"vfrD[43:40] <- sat4u(vfrA[23:16]\\"
	"vfrD[47:44] <- sat4u(vfrA[31:24]\\"
	"vfrD[51:48] <- sat4u(vfrA[39:32]\\"
	"vfrD[55:52] <- sat4u(vfrA[47:40]\\"
	"vfrD[59:56] <- sat4u(vfrA[55:48]\\"
	"vfrD[63:60] <- sat4u(vfrA[63:56]",
	"None", ORVDX64I,},
 
{"lv.packus.h", "Vector Half-word Elements Pack Unsigned Saturated",
	"Lower half of the unsigned halfpword elements of the vector/floating-point register "
	"vfrA are truncated and combined with the lower half of the unsigned half-word "
	"truncated elements of the vector/floating-point register vfrB in such a way "
	"that lowest elements are from vfrB and highest element from vfrA. "
	"If any truncated element exceeds unsigned 8-bit value, it is saturated. "
	"Result elements are placed into vector/floating-point register vfrD.",
	"",
	"vfrD[7:0] <- sat8u(vfrB[15:0])\\"
	"vfrD[15:8] <- sat8u(vfrB[31:16])\\"
	"vfrD[23:16] <- sat8u(vfrB[47:32])\\"
	"vfrD[31:24] <- sat8u(vfrB[63:48])\\"
	"vfrD[39:32] <- sat8u(vfrA[15:0])\\"
	"vfrD[47:40] <- sat8u(vfrA[31:16])\\"
	"vfrD[55:48] <- sat8u(vfrA[47:32])\\"
	"vfrD[63:56] <- sat8u(vfrA[63:48])\\",
	"None", ORVDX64I,},
 
{"lv.unpack.b", "Vector Byte Elements Unpack",
	"Lower half of 4-bit elements in vector/floating-point register "
	"vfrA are sign-extended and placed into vector/floating-point register vfrD.",
	"",
	"vfrD[7:0] <- exts(vfrA[3:0])\\"
	"vfrD[15:8] <- exts(vfrA[7:4])\\"
	"vfrD[23:16] <- exts(vfrA[11:8])\\"
	"vfrD[31:24] <- exts(vfrA[15:12])\\"
	"vfrD[39:32] <- exts(vfrA[19:16])\\"
	"vfrD[47:40] <- exts(vfrA[23:20])\\"
	"vfrD[55:48] <- exts(vfrA[27:24])\\"
	"vfrD[63:56] <- exts(vfrA[31:28])",
	"None", ORVDX64I,},
 
{"lv.unpack.h", "Vector Half-Word Elements Unpack",
	"Lower half of 8-bit elements in vector/floating-point register "
	"vfrA are sign-extended and placed into vector/floating-point register vfrD.",
	"",
	"vfrD[15:0] <- exts(vfrA[7:0])\\"
	"vfrD[31:16] <- exts(vfrA[15:8])\\"
	"vfrD[47:32] <- exts(vfrA[23:16])\\"
	"vfrD[63:48] <- exts(vfrA[31:24])\\",
	"None", ORVDX64I,},
 
{"lv.perm.n", "Vector Nibble Elements Permute",
	"The 4-bit elements of vector/floating-point register vfrA are "
	"permuted according to corresponding 4-bit values in vector/floating-point "
	"register vfrB. "
	"Result elements are placed into vector/floating-point register vfrD.",
	"",
	"vfrD[3:0] <- vfrA[vfrB[3:0]*4+3:vfrB[3:0]*4]\\"
	"vfrD[7:4] <- vfrA[vfrB[7:4]*4+3:vfrB[7:4]*4]\\"
	"vfrD[11:8] <- vfrA[vfrB[11:8]*4+3:vfrB[11:8]*4]\\"
	"vfrD[15:12] <- vfrA[vfrB[15:12]*4+3:vfrB[15:12]*4]\\"
	"vfrD[19:16] <- vfrA[vfrB[19:16]*4+3:vfrB[19:16]*4]\\"
	"vfrD[23:20] <- vfrA[vfrB[23:20]*4+3:vfrB[23:20]*4]\\"
	"vfrD[27:24] <- vfrA[vfrB[27:24]*4+3:vfrB[27:24]*4]\\"
	"vfrD[31:28] <- vfrA[vfrB[31:28]*4+3:vfrB[31:28]*4]\\"
	"vfrD[35:32] <- vfrA[vfrB[35:32]*4+3:vfrB[35:32]*4]\\"
	"vfrD[39:36] <- vfrA[vfrB[39:36]*4+3:vfrB[39:36]*4]\\"
	"vfrD[43:40] <- vfrA[vfrB[43:40]*4+3:vfrB[43:40]*4]\\"
	"vfrD[47:44] <- vfrA[vfrB[47:44]*4+3:vfrB[47:44]*4]\\"
	"vfrD[51:48] <- vfrA[vfrB[51:48]*4+3:vfrB[51:48]*4]\\"
	"vfrD[55:52] <- vfrA[vfrB[55:52]*4+3:vfrB[55:52]*4]\\"
	"vfrD[59:56] <- vfrA[vfrB[59:56]*4+3:vfrB[59:56]*4]\\"
	"vfrD[63:60] <- vfrA[vfrB[63:60]*4+3:vfrB[63:60]*4]",
	"None", ORVDX64I,},
 
{"lv.madds.h", "Vector Half-Word Elements Multiply Add Signed Saturated",
	"The signed half-word elements of vector/floating-point register vfrA are multiplied "
	"by the signed half-word elements of vector/floating-point register vfrB to form "
	"intermediate results. They are added to the signed half-word VMAC elements to "
	"form the final results that are placed again in VMAC registers. "
	"Intermediate result is placed into vector/floating-point register vfrD. "
	"If any of the final results exceeds min/max value, it is saturated.",
	"",
	"vfrD[15:0] <- sat32s(vfrA[15:0] * vfrB[15:0] + VMACLO[31:0])\\"
	"vfrD[31:16] <- sat32s(vfrA[31:16] * vfrB[31:16] + VMACLO[63:32])\\"
	"vfrD[47:32] <- sat32s(vfrA[47:32] * vfrB[47:32] + VMACHI[31:0])\\"
	"vfrD[63:48] <- sat32s(vfrA[63:48] * vfrB[63:48] + VMACHI[63:32])\\",
	"None", ORVDX64I,},
 
{"lv.msubs.h", "Vector Half-Word Elements Multiply Subtract Signed Saturated",
	"The signed half-word elements of vector/floating-point register vfrA are multiplied "
	"by the signed half-word elements of vector/floating-point register vfrB to form "
	"intermediate results. They are subtracted from the signed half-word VMAC elements to "
	"form the final results that are placed again in VMAC registers. "
	"Intermediate result is placed into vector/floating-point register vfrD. "
	"If any of the final results exceeds min/max value, it is saturated.",
	"",
	"vfrD[15:0] <- sat32s(VMACLO[31:0] - vfrA[15:0] * vfrB[15:0])\\"
	"vfrD[31:16] <- sat32s(VMACLO[63:32] - vfrA[31:16] * vfrB[31:16])\\"
	"vfrD[47:32] <- sat32s(VMACHI[31:0] - vfrA[47:32] * vfrB[47:32])\\"
	"vfrD[63:48] <- sat32s(VMACHI[63:32] - vfrA[63:48] * vfrB[63:48])\\",
	"None", ORVDX64I,},
 
{"lv.muls.h", "Vector Half-Word Elements Multiply Signed Saturated",
	"The signed half-word elements of vector/floating-point register vfrA are multiplied "
	"by the signed half-word elements of vector/floating-point register vfrB to form "
	"the results. "
	"The result is placed into vector/floating-point register vfrD. "
	"If any of the final results exceeds min/max value, it is saturated.",
	"",
	"vfrD[15:0] <- sat32s(vfrA[15:0] * vfrB[15:0])\\"
	"vfrD[31:16] <- sat32s(vfrA[31:16] * vfrB[31:16])\\"
	"vfrD[47:32] <- sat32s(vfrA[47:32] * vfrB[47:32])\\"
	"vfrD[63:48] <- sat32s(vfrA[63:48] * vfrB[63:48])\\",
	"None", ORVDX64II,},
 
{"lv.cust1", "Reserved for Custom Vector Instructions",
	"This fake instruction only allocates instruction set space for custom instructions. "
	"Custom instructions are those that are not defined by the architecture, but instead "
	"by the implementation itself.",
	"N/A",
	"N/A",
	"N/A", ORVDX64II,},
 
{"lv.cust2", "Reserved for Custom Vector Instructions",
	"This fake instruction only allocates instruction set space for custom instructions. "
	"Custom instructions are those that are not defined by the architecture, but instead "
	"by the implementation itself.",
	"N/A",
	"N/A",
	"N/A", ORVDX64II,},
 
{"lv.cust3", "Reserved for Custom Vector Instructions",
	"This fake instruction only allocates instruction set space for custom instructions. "
	"Custom instructions are those that are not defined by the architecture, but instead "
	"by the implementation itself.",
	"N/A",
	"N/A",
	"N/A", ORVDX64II,},
 
{"lv.cust4", "Reserved for Custom Vector Instructions",
	"This fake instruction only allocates instruction set space for custom instructions. "
	"Custom instructions are those that are not defined by the architecture, but instead "
	"by the implementation itself.",
	"N/A",
	"N/A",
	"N/A", ORVDX64II,},
 
/**** L/S for ORFPX/ORVDX ***/
 
{"lvf.ld", "Load Vector/Floating-Point Double Word",
	"The contents of vector/floating-point "
	"register vfrA is used as effective address. The double word in memory "
	"addressed by EA is loaded into vector/floating-point register vfrD. ",
	"N/A",
	"EA <- vfrA[63:0]\\rD[63:0] <- (EA)[63:0]",
	"TLB miss\\Page fault\\Bus error", ORFPX64I,},
 
{"lvf.lw", "Load Vector/Floating-Point Single Word",
	"The contents of vector/floating-point "
	"register vfrA is used as effective address. The double word in memory "
	"addressed by EA is loaded into vector/floating-point register vfrD. ",
	"EA <- vfrA[31:0]\\rD[31:0] <- (EA)[31:0]",
	"EA <- vfrA[31:0]\\rD[31:0] <- (EA)[31:0]",
	"TLB miss\\Page fault\\Bus error", ORFPX32I,},
 
{"lvf.sd", "Store Vector/Floating-Point Double Word",
	"The contents of vector/floating-point "
	"register vfrA is used as effective address. The double word in vector/floating-point "
	"register vrfB is stored to memory location addresses by EA. ",
	"N/A",
	"EA <- vfrA[63:0]\\rD[63:0] <- (EA)[63:0]",
	"TLB miss\\Page fault\\Bus error", ORFPX64I,},
 
{"lvf.sw", "Store Vector/Floating-Point Single Word",
	"The contents of vector/floating-point "
	"register vfrA is used as effective address. The single word in vector/floating-point "
	"register vrfB is stored to memory location addresses by EA. ",
	"EA <- vfrA[31:0]\\rD[31:0] <- (EA)[31:0]",
	"EA <- vfrA[31:0]\\rD[31:0] <- (EA)[31:0]",
	"TLB miss\\Page fault\\Bus error", ORFPX32I,},
 
{"", "", "", "", "", "", 0}
 
};
 
struct or1k_isa_classes {
	char *title;
	char *desc;
	char *table;
} or1k_isa_classes[] = {
 
{ "", "x", "-&-\\", },
{ "", "x", "ORBIS32 I&Required\\", },
{ "", "x", "ORBIS32 II&Optional\\", },
{ "", "x", "ORBIS64 I&Required\\", },
{ "", "x", "ORBIS64 II&Optional\\", },
{ "", "x", "ORFPX32 I&Required\\", },
{ "", "x", "ORFPX32 II&Optional\\", },
{ "", "x", "ORFPX64 I&Required\\", },
{ "", "x", "ORFPX64 II&Optional\\", },
{ "", "x", "ORVDX64 I&Required\\", },
{ "", "x", "ORVDX64 II&Optional\\", },
{ "", "x", "&\\", },
 
};
 
struct or1k_order {
	char *title;
	unsigned long classes;
} or1k_order[] = {
 
{ "ORBIS32/64", (1<<ORBIS32I)>>1 | (1<<ORBIS32II)>>1 | (1<<ORBIS64I)>>1 | (1<<ORBIS64II)>>1, },
{ "ORFPX32/64", (1<<ORFPX32I)>>1 | (1<<ORFPX32II)>>1 | (1<<ORFPX64I)>>1 | (1<<ORFPX64II)>>1, },
{ "ORVDX64", (1<<ORVDX64I)>>1 | (1<<ORVDX64II)>>1, },
{ "", 0, },
 
};