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# fr30 testcase for mulu $Rj,$Ri
# mach(): fr30

        .include "testutils.inc"

        START

        .text
        .global mulu
mulu:
        ; Test mulu $Rj,$Ri
        ; Positive operands
        mvi_h_gr        3,r7            ; multiply small numbers
        mvi_h_gr        2,r8
        set_cc          0x0f            ; Set mask opposite of expected
        mulu            r7,r8
        test_cc         0 0 0 1
        test_h_dr       0,mdh
        test_h_dr       6,mdl

        mvi_h_gr        1,r7            ; multiply by 1
        mvi_h_gr        2,r8
        set_cc          0x0e            ; Set mask opposite of expected
        mulu            r7,r8
        test_cc         0 0 0 0
        test_h_dr       0,mdh
        test_h_dr       2,mdl

        mvi_h_gr        2,r7            ; multiply by 1
        mvi_h_gr        1,r8
        set_cc          0x0f            ; Set mask opposite of expected
        mulu            r7,r8
        test_cc         0 0 0 1
        test_h_dr       0,mdh
        test_h_dr       2,mdl

        mvi_h_gr        0,r7            ; multiply by 0
        mvi_h_gr        2,r8
        set_cc          0x0b            ; Set mask opposite of expected
        mulu            r7,r8
        test_cc         0 1 0 1
        test_h_dr       0,mdh
        test_h_dr       0,mdl

        mvi_h_gr        2,r7            ; multiply by 0
        mvi_h_gr        0,r8
        set_cc          0x0a            ; Set mask opposite of expected
        mulu            r7,r8
        test_cc         0 1 0 0
        test_h_dr       0,mdh
        test_h_dr       0,mdl

        mvi_h_gr        0x3fffffff,r7   ; 31 bit result
        mvi_h_gr        2,r8
        set_cc          0x0f            ; Set mask opposite of expected
        mulu            r7,r8
        test_cc         0 0 0 1
        test_h_dr       0,mdh
        test_h_dr       0x7ffffffe,mdl

        mvi_h_gr        0x40000000,r7   ; 32 bit result
        mvi_h_gr        2,r8
        set_cc          0x0e            ; Set mask opposite of expected
        mulu            r7,r8
        test_cc         0 0 0 0
        test_h_dr       0,mdh
        test_h_dr       0x80000000,mdl

        mvi_h_gr        0x80000000,r7   ; 33 bit result
        mvi_h_gr        2,r8
        set_cc          0x09            ; Set mask opposite of expected
        mulu            r7,r8
        test_cc         0 1 1 1
        test_h_dr       1,mdh
        test_h_dr       0x00000000,mdl

        mvi_h_gr        0x7fffffff,r7   ; max positive result
        mvi_h_gr        0x7fffffff,r8
        set_cc          0x0d            ; Set mask opposite of expected
        mulu            r7,r8
        test_cc         0 0 1 1
        test_h_dr       0x3fffffff,mdh
        test_h_dr       0x00000001,mdl

        mvi_h_gr        0x80000000,r7   ; max positive result
        mvi_h_gr        0x80000000,r8
        set_cc          0x09            ; Set mask opposite of expected
        mulu            r7,r8
        test_cc         0 1 1 1
        test_h_dr       0x40000000,mdh
        test_h_dr       0x00000000,mdl

        mvi_h_gr        0xffffffff,r7   ; max positive result
        mvi_h_gr        0xffffffff,r8
        set_cc          0x05            ; Set mask opposite of expected
        mulu            r7,r8
        test_cc         1 0 1 1
        test_h_dr       0xfffffffe,mdh
        test_h_dr       0x00000001,mdl

        pass