OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [jtag/] [jp2.h] - Rev 1781

Go to most recent revision | Compare with Previous | Blame | View Log

#ifndef _JP2_H_
#define _JP2_H_
 
#define Boolean int
#define false 0
#define true 1
 
/* Selects crc trailer size in bits. Currently supported: 8 */
#define CRC_SIZE (8)
 
/* Scan chain size in bits.  */
#define SC_SIZE (4)
 
#ifndef ULONGEST
#define ULONGEST unsigned long
#endif
 
extern unsigned int serverPort;
extern unsigned int server_fd;
extern void HandleServerSocket(Boolean block);
 
extern int err;
extern void JTAGRequest(void);
extern void GDBRequest(void);
 
/* read a word from wishbone */
int dbg_wb_read32(unsigned long adr, unsigned long *data);
 
/* write a word to wishbone */
int dbg_wb_write32(unsigned long adr, unsigned long data);
 
/* read a block from wishbone */
int dbg_wb_read_block32(unsigned long adr, unsigned long *data, int len);
 
/* write a block to wishbone */
int dbg_wb_write_block32(unsigned long adr, unsigned long *data, int len);
 
/* read a register from cpu */
int dbg_cpu0_read(unsigned long adr, unsigned long *data);
 
/* read a register from cpu module */
int dbg_cpu0_read_ctrl(unsigned long adr, unsigned char *data);
 
/* write a cpu register */
int dbg_cpu0_write(unsigned long adr, unsigned long data);
 
/* write a cpu module register */
int dbg_cpu0_write_ctrl(unsigned long adr, unsigned char data);
 
 
#define DC_SIZE           4
#define DC_STATUS_SIZE    4
 
#define DC_WISHBONE       0
#define DC_CPU0           1
#define DC_CPU1           2
 
#define DI_GO          0
#define DI_READ_CMD    1
#define DI_WRITE_CMD   2
#define DI_READ_CTRL   3
#define DI_WRITE_CTRL  4
 
#define DBG_CRC_SIZE      32
#define DBG_CRC_POLY      0x04c11db7
 
#define DBG_ERR_OK        0
#define DBG_ERR_CRC       8
 
#define NUM_SOFT_RETRIES  3
#define NUM_HARD_RETRIES  3
#define NUM_ACCESS_RETRIES 10
 
#define CHECK(x) check(__FILE__, __LINE__, (x))
#endif /* _JP2_H_ */
 
 

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.