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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [arch/] [arm/] [kernel/] [debug-armv.S] - Rev 1765
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/** linux/arch/arm/kernel/debug-armv.S** Copyright (C) 1994-1999 Russell King** This program is free software; you can redistribute it and/or modify* it under the terms of the GNU General Public License version 2 as* published by the Free Software Foundation.** 32-bit debugging code*/#include <linux/config.h>#include <linux/linkage.h>#include <asm/hardware.h>.text/** Some debugging routines (useful if you've got MM problems and* printk isn't working). For DEBUGGING ONLY!!! Do not leave* references to these in a production kernel!*/#if defined(CONFIG_ARCH_RPC) || defined(CONFIG_ARCH_RISCSTATION).macro addruart,rx/* note, errors can occur in the head code BEFORE the memory map has been* setup (and therefore the mapping for the IO) so the #if statement allows* the address of the uart to be changed to the physical address instead of* the logical** (bjd)*/mrc p15, 0, \rx, c1, c0tst \rx, #1 @ MMU enabled?movne \rx, #0xe0000000moveq \rx, #0x03000000orr \rx, \rx, #0x00010000orr \rx, \rx, #0x00000fe0.endm.macro senduart,rd,rxstrb \rd, [\rx].endm.macro busyuart,rd,rx1001: ldrb \rd, [\rx, #0x14]and \rd, \rd, #0x60teq \rd, #0x60bne 1001b.endm.macro waituart,rd,rx1001: ldrb \rd, [\rx, #0x18]tst \rd, #0x10beq 1001b.endm#elif defined(CONFIG_ARCH_EBSA110).macro addruart,rxmov \rx, #0xf0000000orr \rx, \rx, #0x00000be0.endm.macro senduart,rd,rxstrb \rd, [\rx].endm.macro busyuart,rd,rx1002: ldrb \rd, [\rx, #0x14]and \rd, \rd, #0x60teq \rd, #0x60bne 1002b.endm.macro waituart,rd,rx1001: ldrb \rd, [\rx, #0x18]tst \rd, #0x10beq 1001b.endm#elif defined(CONFIG_ARCH_SHARK).macro addruart,rxmov \rx, #0xe0000000orr \rx, \rx, #0x000003f8.endm.macro senduart,rd,rxstrb \rd, [\rx].endm.macro busyuart,rd,rxmov \rd, #01001: add \rd, \rd, #1teq \rd, #0x10000bne 1001b.endm.macro waituart,rd,rx.endm#elif defined(CONFIG_FOOTBRIDGE)#include <asm/hardware/dec21285.h>#ifndef CONFIG_DEBUG_DC21285_PORT/* For NetWinder debugging */.macro addruart,rxmrc p15, 0, \rx, c1, c0tst \rx, #1 @ MMU enabled?moveq \rx, #0x7c000000 @ physicalmovne \rx, #0xff000000 @ virtualorr \rx, \rx, #0x000003f8.endm.macro senduart,rd,rxstrb \rd, [\rx].endm.macro busyuart,rd,rx1002: ldrb \rd, [\rx, #0x5]and \rd, \rd, #0x60teq \rd, #0x60bne 1002b.endm.macro waituart,rd,rx1001: ldrb \rd, [\rx, #0x6]tst \rd, #0x10beq 1001b.endm#else/* For EBSA285 debugging */.equ dc21285_high, ARMCSR_BASE & 0xff000000.equ dc21285_low, ARMCSR_BASE & 0x00ffffff.macro addruart,rxmov \rx, #dc21285_high.if dc21285_loworr \rx, \rx, #dc21285_low.endif.endm.macro senduart,rd,rxstr \rd, [\rx, #0x160] @ UARTDR.endm.macro busyuart,rd,rx1001: ldr \rd, [\rx, #0x178] @ UARTFLGtst \rd, #1 << 3bne 1001b.endm.macro waituart,rd,rx.endm#endif#elif defined(CONFIG_ARCH_FTVPCI).macro addruart,rxmrc p15, 0, \rx, c1, c0tst \rx, #1 @ MMU enabled?movne \rx, #0xe0000000moveq \rx, #0x10000000.endm.macro senduart,rd,rxstr \rd, [\rx, #0xc].endm.macro busyuart,rd,rx1001: ldr \rd, [\rx, #0x4]tst \rd, #1 << 2beq 1001b.endm.macro waituart,rd,rx.endm#elif defined(CONFIG_ARCH_SA1100).macro addruart,rxmrc p15, 0, \rx, c1, c0tst \rx, #1 @ MMU enabled?moveq \rx, #0x80000000 @ physical base addressmovne \rx, #0xf8000000 @ virtual address@ We probe for the active serial port here, coherently with@ the comment in include/asm-arm/arch-sa1100/uncompress.h.@ We assume r1 can be clobbered.@ see if Ser3 is activeadd \rx, \rx, #0x00050000ldr r1, [\rx, #UTCR3]tst r1, #UTCR3_TXE@ if Ser3 is inactive, then try Ser1addeq \rx, \rx, #(0x00010000 - 0x00050000)ldreq r1, [\rx, #UTCR3]tsteq r1, #UTCR3_TXE@ if Ser1 is inactive, then try Ser2addeq \rx, \rx, #(0x00030000 - 0x00010000)ldreq r1, [\rx, #UTCR3]tsteq r1, #UTCR3_TXE@ if all ports are inactive, then there is nothing we can domoveq pc, lr.endm.macro senduart,rd,rxstr \rd, [\rx, #UTDR].endm.macro waituart,rd,rx1001: ldr \rd, [\rx, #UTSR1]tst \rd, #UTSR1_TNFbeq 1001b.endm.macro busyuart,rd,rx1001: ldr \rd, [\rx, #UTSR1]tst \rd, #UTSR1_TBYbne 1001b.endm#elif defined(CONFIG_ARCH_CLPS7500).macro addruart,rxmov \rx, #0xe0000000orr \rx, \rx, #0x00010000orr \rx, \rx, #0x00000be0.endm.macro senduart,rd,rxstrb \rd, [\rx].endm.macro busyuart,rd,rx.endm.macro waituart,rd,rx1001: ldrb \rd, [\rx, #0x14]tst \rd, #0x20beq 1001b.endm#elif defined(CONFIG_ARCH_L7200).equ io_virt, IO_BASE.equ io_phys, IO_START.macro addruart,rxmrc p15, 0, \rx, c1, c0tst \rx, #1 @ MMU enabled?moveq \rx, #io_phys @ physical base addressmovne \rx, #io_virt @ virtual addressadd \rx, \rx, #0x00044000 @ UART1@ add \rx, \rx, #0x00045000 @ UART2.endm.macro senduart,rd,rxstr \rd, [\rx, #0x0] @ UARTDR.endm.macro waituart,rd,rx1001: ldr \rd, [\rx, #0x18] @ UARTFLGtst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when fullbne 1001b.endm.macro busyuart,rd,rx1001: ldr \rd, [\rx, #0x18] @ UARTFLGtst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busybne 1001b.endm#elif defined(CONFIG_ARCH_INTEGRATOR)#include <asm/hardware/serial_amba.h>.macro addruart,rxmrc p15, 0, \rx, c1, c0tst \rx, #1 @ MMU enabled?moveq \rx, #0x16000000 @ physical base addressmovne \rx, #0xf0000000 @ virtual baseaddne \rx, \rx, #0x16000000 >> 4.endm.macro senduart,rd,rxstrb \rd, [\rx, #AMBA_UARTDR].endm.macro waituart,rd,rx1001: ldr \rd, [\rx, #0x18] @ UARTFLGtst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when fullbne 1001b.endm.macro busyuart,rd,rx1001: ldr \rd, [\rx, #0x18] @ UARTFLGtst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busybne 1001b.endm#elif defined(CONFIG_ARCH_AT91RM9200).macro addruart,rxmrc p15, 0, \rx, c1, c0tst \rx, #1 @ MMU enabled?ldreq \rx, =AT91C_BASE_SYS @ System peripherals (phys address)ldrne \rx, =AT91C_VA_BASE_SYS @ System peripherals (virt address).endm.macro senduart,rd,rxstrb \rd, [\rx, #DBGU_THR] @ DBGU_THR.endm.macro waituart,rd,rx1001: ldr \rd, [\rx, #DBGU_CSR] @ DBGU_CSRtst \rd, #AT91C_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmitbeq 1001b.endm.macro busyuart,rd,rx1001: ldr \rd, [\rx, #DBGU_CSR] @ DBGU_CSRtst \rd, #AT91C_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission completebeq 1001b.endm#elif defined(CONFIG_ARCH_CLPS711X)#include <asm/hardware/clps7111.h>.macro addruart,rxmrc p15, 0, \rx, c1, c0tst \rx, #1 @ MMU enabled?moveq \rx, #CLPS7111_PHYS_BASEmovne \rx, #CLPS7111_VIRT_BASE#ifndef CONFIG_DEBUG_CLPS711X_UART2add \rx, \rx, #0x0000 @ UART1#elseadd \rx, \rx, #0x1000 @ UART2#endif.endm.macro senduart,rd,rxstr \rd, [\rx, #0x0480] @ UARTDR.endm.macro waituart,rd,rx1001: ldr \rd, [\rx, #0x0140] @ SYSFLGxtst \rd, #1 << 11 @ UBUSYxbne 1001b.endm.macro busyuart,rd,rxtst \rx, #0x1000 @ UART2 does not have CTS herebne 1002f1001: ldr \rd, [\rx, #0x0140] @ SYSFLGxtst \rd, #1 << 8 @ CTSbne 1001b1002:.endm#elif defined(CONFIG_ARCH_OMAHA)#include <asm/hardware/serial_omaha.h>.macro addruart,rx.endm.macro senduart,rd,rx.endm.macro waituart,rd,rx.endm.macro busyuart,rd,rx.endm#elif defined(CONFIG_ARCH_ANAKIN)//#//include <asm/arch/serial_reg.h>.macro addruart,rxmrc p15, 0, \rx, c1, c0tst \rx, #1 @ MMU enabled?moveq \rx, #IO_STARTmovne \rx, #IO_BASEadd \rx, \rx, #UART0.endm.macro senduart,rd,rxstr \rd, [\rx, #0x14] @ txldr \rd, [\rx, #0x18]orr \rd, \rd, #SENDREQUESTstr \rd, [\rx, #0x18].endm.macro waituart,rd,rx1001: ldr \rd, [\rx, #0x10]tst \rd, #TXEMPTYbeq 1001b.endm.macro busyuart,rd,rx1001: ldr \rd, [\rx, #0x10]tst \rd, #CTSbne 1001b.endm#elif defined(CONFIG_ARCH_CAMELOT)#include <asm/arch/excalibur.h>#define UART00_TYPE#include <asm/arch/uart00.h>.macro addruart,rxmrc p15, 0, \rx, c1, c0tst \rx, #1 @ MMU enabled?ldr \rx, =EXC_UART00_BASE @ physical base addressorrne \rx, \rx, #0xff000000 @ virtual baseorrne \rx, \rx, #0x00f00000.endm.macro senduart,rd,rxstr \rd, [\rx, #UART_TD(0)].endm.macro waituart,rd,rx1001: ldr \rd, [\rx, #UART_TSR(0)]and \rd, \rd, #UART_TSR_TX_LEVEL_MSKcmp \rd, #15beq 1001b.endm.macro busyuart,rd,rx1001: ldr \rd, [\rx, #UART_TSR(0)]ands \rd, \rd, #UART_TSR_TX_LEVEL_MSKbne 1001b.endm#elif defined(CONFIG_ARCH_MX1ADS).macro addruart,rxmrc p15, 0, \rx, c1, c0tst \rx, #1 @ MMU enabled?moveq \rx, #0x00000000 @ physicalmovne \rx, #0xf0000000 @ virtualorr \rx, \rx, #0x00200000orr \rx, \rx, #0x00006000 @ UART1 offset.endm.macro senduart,rd,rxstr \rd, [\rx, #0x40] @ TXDATA.endm.macro waituart,rd,rx#if 0/* REVISIT: This isn't right. I believe we should be checking CTS here instead* to see if the user has entered <CTRL><S> to pause console output.* gdavis@mvista.com 28apr03*/1001: ldr \rd, [\rx, #0x94] @ SR1tst \rd, #1 << 13 @ TRDYbne 1001b @ wait until TX FIFO ready#endif.endm.macro busyuart,rd,rx1002: ldr \rd, [\rx, #0x98] @ SR2tst \rd, #1 << 3 @ TXDCbeq 1002b @ wait until transmit done.endm#else#error Unknown architecture#endif/** Useful debugging routines*/ENTRY(printhex8)mov r1, #8b printhexENTRY(printhex4)mov r1, #4b printhexENTRY(printhex2)mov r1, #2printhex: adr r2, hexbufadd r3, r2, r1mov r1, #0strb r1, [r3]1: and r1, r0, #15mov r0, r0, lsr #4cmp r1, #10addlt r1, r1, #'0'addge r1, r1, #'a' - 10strb r1, [r3, #-1]!teq r3, r2bne 1bmov r0, r2b printascii.ltorgENTRY(printascii)addruart r3b 2f1: waituart r2, r3senduart r1, r3busyuart r2, r3teq r1, #'\n'moveq r1, #'\r'beq 1b2: teq r0, #0ldrneb r1, [r0], #1teqne r1, #0bne 1bmov pc, lrENTRY(printch)addruart r3mov r1, r0mov r0, #0b 1bhexbuf: .space 16