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/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1996, 1998, 2000 by Ralf Baechle
 *
 * Multi-arch abstraction and asm macros for easier reading:
 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
 *
 *  Carsten Langgaard, carstenl@mips.com
 *  Copyright (C) 2000 MIPS Technologies, Inc.
 */
#include <asm/asm.h>
#include <asm/errno.h>
#include <asm/fpregdef.h>
#include <asm/mipsregs.h>
#include <asm/offset.h>
#include <asm/regdef.h>

#define EX(a,b)                                                 \
9:      a,b;                                                    \
        .section __ex_table,"a";                                \
        PTR     9b, fault;                                      \
        .previous

        .set    noreorder
        .set    mips3
        /* Save floating point context */
LEAF(_save_fp_context)
        li      v0, 0                                   # assume success
        cfc1    t1,fcr31

        /* Store the 16 even double precision registers */
        EX(sdc1 $f0,(SC_FPREGS+0)(a0))
        EX(sdc1 $f2,(SC_FPREGS+16)(a0))
        EX(sdc1 $f4,(SC_FPREGS+32)(a0))
        EX(sdc1 $f6,(SC_FPREGS+48)(a0))
        EX(sdc1 $f8,(SC_FPREGS+64)(a0))
        EX(sdc1 $f10,(SC_FPREGS+80)(a0))
        EX(sdc1 $f12,(SC_FPREGS+96)(a0))
        EX(sdc1 $f14,(SC_FPREGS+112)(a0))
        EX(sdc1 $f16,(SC_FPREGS+128)(a0))
        EX(sdc1 $f18,(SC_FPREGS+144)(a0))
        EX(sdc1 $f20,(SC_FPREGS+160)(a0))
        EX(sdc1 $f22,(SC_FPREGS+176)(a0))
        EX(sdc1 $f24,(SC_FPREGS+192)(a0))
        EX(sdc1 $f26,(SC_FPREGS+208)(a0))
        EX(sdc1 $f28,(SC_FPREGS+224)(a0))
        EX(sdc1 $f30,(SC_FPREGS+240)(a0))
        EX(sw   t1,SC_FPC_CSR(a0))
        cfc1    t0,$0                           # implementation/version

        jr      ra
        .set    nomacro
         EX(sw  t0,SC_FPC_EIR(a0))
        .set    macro
        END(_save_fp_context)

/*
 * Restore FPU state:
 *  - fp gp registers
 *  - cp1 status/control register
 *
 * We base the decision which registers to restore from the signal stack
 * frame on the current content of c0_status, not on the content of the
 * stack frame which might have been changed by the user.
 */
LEAF(_restore_fp_context)
        li      v0, 0                                   # assume success
        EX(lw   t0,SC_FPC_CSR(a0))

        /*
         * Restore the 16 even double precision registers
         * when cp1 was enabled in the cp0 status register.
         */
        EX(ldc1 $f0,(SC_FPREGS+0)(a0))
        EX(ldc1 $f2,(SC_FPREGS+16)(a0))
        EX(ldc1 $f4,(SC_FPREGS+32)(a0))
        EX(ldc1 $f6,(SC_FPREGS+48)(a0))
        EX(ldc1 $f8,(SC_FPREGS+64)(a0))
        EX(ldc1 $f10,(SC_FPREGS+80)(a0))
        EX(ldc1 $f12,(SC_FPREGS+96)(a0))
        EX(ldc1 $f14,(SC_FPREGS+112)(a0))
        EX(ldc1 $f16,(SC_FPREGS+128)(a0))
        EX(ldc1 $f18,(SC_FPREGS+144)(a0))
        EX(ldc1 $f20,(SC_FPREGS+160)(a0))
        EX(ldc1 $f22,(SC_FPREGS+176)(a0))
        EX(ldc1 $f24,(SC_FPREGS+192)(a0))
        EX(ldc1 $f26,(SC_FPREGS+208)(a0))
        EX(ldc1 $f28,(SC_FPREGS+224)(a0))
        EX(ldc1 $f30,(SC_FPREGS+240)(a0))
        jr      ra
         ctc1   t0,fcr31
        END(_restore_fp_context)
        .set    reorder

        .type   fault@function
        .ent    fault
fault:  li      v0, -EFAULT
        jr      ra
        .end    fault