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;; Purpose:; This file has the overall purpose of suppyling low-level; assembly to program the intrigue portion of the cpu.;#include <linux/config.h>#include <asm/assembly.h>#ifdef __LP64__.level 2.0w#endif /* __LP64__ */#define MTDIAG_1(gr) .word 0x14201840 + gr*0x10000#define MTDIAG_2(gr) .word 0x14401840 + gr*0x10000#define MFDIAG_1(gr) .word 0x142008A0 + gr#define MFDIAG_2(gr) .word 0x144008A0 + gr#define STDIAG(dr) .word 0x14000AA0 + dr*0x200000#define SFDIAG(dr) .word 0x14000BA0 + dr*0x200000#define DR2_SLOW_RET 53;; Enable the performance counters;; The coprocessor only needs to be enabled when; starting/stopping the coprocessor with the pmenb/pmdis.;.text.align 32.export perf_intrigue_enable_perf_counters,codeperf_intrigue_enable_perf_counters:.proc.callinfo frame=0,NO_CALLS.entryldi 0x20,%r25 ; load up perfmon bitmfctl ccr,%r26 ; get coprocessor registeror %r25,%r26,%r26 ; set bitmtctl %r26,ccr ; turn on performance coprocessorpmenb ; enable performance monitorssm 0,0 ; dummy op to ensure completionsync ; follow ERSandcm %r26,%r25,%r26 ; clear bit nowmtctl %r26,ccr ; turn off performance coprocessornop ; NOPs as specified in ERSnopnopnopnopnopnopbve (%r2)nop.exit.procend.export perf_intrigue_disable_perf_counters,codeperf_intrigue_disable_perf_counters:.proc.callinfo frame=0,NO_CALLS.entryldi 0x20,%r25 ; load up perfmon bitmfctl ccr,%r26 ; get coprocessor registeror %r25,%r26,%r26 ; set bitmtctl %r26,ccr ; turn on performance coprocessorpmdis ; disable performance monitorssm 0,0 ; dummy op to ensure completionandcm %r26,%r25,%r26 ; clear bit nowbve (%r2)mtctl %r26,ccr ; turn off performance coprocessor.exit.procend;************************************************************************;* *;* Name: perf_rdr_shift_in_W *;* *;* Description: *;* This routine shifts data in from the RDR in arg0 and returns *;* the result in ret0. If the RDR is <= 64 bits in length, it *;* is shifted shifted backup immediately. This is to compensate *;* for RDR10 which has bits that preclude PDC stack operations *;* when they are in the wrong state. *;* *;* Arguments: *;* arg0 : rdr to be read *;* arg1 : bit length of rdr *;* *;* Returns: *;* ret0 = next 64 bits of rdr data from staging register *;* *;* Register usage: *;* arg0 : rdr to be read *;* arg1 : bit length of rdr *;* %r24 - original DR2 value *;* %r1 - scratch *;* %r29 - scratch *;* *;* Returns: *;* ret0 = RDR data (right justified) *;* *;************************************************************************.export perf_rdr_shift_in_W,codeperf_rdr_shift_in_W:.proc.callinfo frame=0,NO_CALLS.entry;; read(shift in) the RDR.;; NOTE: The PCX-W ERS states that DR2_SLOW_RET must be set before any; shifting is done, from or to, remote diagnose registers.;depdi,z 1,DR2_SLOW_RET,1,%r29MFDIAG_2 (24)or %r24,%r29,%r29MTDIAG_2 (29) ; set DR2_SLOW_RETnopnopnopnop;; Cacheline start (32-byte cacheline);nopnopnopextrd,u arg1,63,6,%r1 ; setup shift amount based on bits to movemtsar %r1shladd arg0,2,%r0,%r1 ; %r1 = 4 * RDR numberblr %r1,%r0 ; branch to 8-instruction sequencenop;; Cacheline start (32-byte cacheline);;; RDR 0 sequence;SFDIAG (0)ssm 0,0MFDIAG_1 (28)shrpd ret0,%r0,%sar,%r1MTDIAG_1 (1) ; mtdiag %dr1, %r1STDIAG (0)ssm 0,0b,n perf_rdr_shift_in_W_leave;; RDR 1 sequence;syncssm 0,0SFDIAG (1)ssm 0,0MFDIAG_1 (28)ssm 0,0b,n perf_rdr_shift_in_W_leavenop;; RDR 2 read sequence;SFDIAG (2)ssm 0,0MFDIAG_1 (28)shrpd ret0,%r0,%sar,%r1MTDIAG_1 (1)STDIAG (2)ssm 0,0b,n perf_rdr_shift_in_W_leave;; RDR 3 read sequence;b,n perf_rdr_shift_in_W_leavenopnopnopnopnopnopnop;; RDR 4 read sequence;syncssm 0,0SFDIAG (4)ssm 0,0MFDIAG_1 (28)b,n perf_rdr_shift_in_W_leavessm 0,0nop;; RDR 5 read sequence;syncssm 0,0SFDIAG (5)ssm 0,0MFDIAG_1 (28)b,n perf_rdr_shift_in_W_leavessm 0,0nop;; RDR 6 read sequence;syncssm 0,0SFDIAG (6)ssm 0,0MFDIAG_1 (28)b,n perf_rdr_shift_in_W_leavessm 0,0nop;; RDR 7 read sequence;b,n perf_rdr_shift_in_W_leavenopnopnopnopnopnopnop;; RDR 8 read sequence;b,n perf_rdr_shift_in_W_leavenopnopnopnopnopnopnop;; RDR 9 read sequence;b,n perf_rdr_shift_in_W_leavenopnopnopnopnopnopnop;; RDR 10 read sequence;SFDIAG (10)ssm 0,0MFDIAG_1 (28)shrpd ret0,%r0,%sar,%r1MTDIAG_1 (1)STDIAG (10)ssm 0,0b,n perf_rdr_shift_in_W_leave;; RDR 11 read sequence;SFDIAG (11)ssm 0,0MFDIAG_1 (28)shrpd ret0,%r0,%sar,%r1MTDIAG_1 (1)STDIAG (11)ssm 0,0b,n perf_rdr_shift_in_W_leave;; RDR 12 read sequence;b,n perf_rdr_shift_in_W_leavenopnopnopnopnopnopnop;; RDR 13 read sequence;syncssm 0,0SFDIAG (13)ssm 0,0MFDIAG_1 (28)b,n perf_rdr_shift_in_W_leavessm 0,0nop;; RDR 14 read sequence;SFDIAG (14)ssm 0,0MFDIAG_1 (28)shrpd ret0,%r0,%sar,%r1MTDIAG_1 (1)STDIAG (14)ssm 0,0b,n perf_rdr_shift_in_W_leave;; RDR 15 read sequence;sync ; RDR 15 read sequencessm 0,0SFDIAG (15)ssm 0,0MFDIAG_1 (28)ssm 0,0b,n perf_rdr_shift_in_W_leavenop;; RDR 16 read sequence;sync ; RDR 16 read sequencessm 0,0SFDIAG (16)ssm 0,0MFDIAG_1 (28)b,n perf_rdr_shift_in_W_leavessm 0,0nop;; RDR 17 read sequence;SFDIAG (17)ssm 0,0MFDIAG_1 (28)shrpd ret0,%r0,%sar,%r1MTDIAG_1 (1)STDIAG (17)ssm 0,0b,n perf_rdr_shift_in_W_leave;; RDR 18 read sequence;SFDIAG (18)ssm 0,0MFDIAG_1 (28)shrpd ret0,%r0,%sar,%r1MTDIAG_1 (1)STDIAG (18)ssm 0,0b,n perf_rdr_shift_in_W_leave;; RDR 19 read sequence;b,n perf_rdr_shift_in_W_leavenopnopnopnopnopnopnop;; RDR 20 read sequence;syncssm 0,0SFDIAG (20)ssm 0,0MFDIAG_1 (28)b,n perf_rdr_shift_in_W_leavessm 0,0nop;; RDR 21 read sequence;syncssm 0,0SFDIAG (21)ssm 0,0MFDIAG_1 (28)b,n perf_rdr_shift_in_W_leavessm 0,0nop;; RDR 22 read sequence;syncssm 0,0SFDIAG (22)ssm 0,0MFDIAG_1 (28)b,n perf_rdr_shift_in_W_leavessm 0,0nop;; RDR 23 read sequence;syncssm 0,0SFDIAG (23)ssm 0,0MFDIAG_1 (28)b,n perf_rdr_shift_in_W_leavessm 0,0nop;; RDR 24 read sequence;syncssm 0,0SFDIAG (24)ssm 0,0MFDIAG_1 (28)b,n perf_rdr_shift_in_W_leavessm 0,0nop;; RDR 25 read sequence;syncssm 0,0SFDIAG (25)ssm 0,0MFDIAG_1 (28)b,n perf_rdr_shift_in_W_leavessm 0,0nop;; RDR 26 read sequence;SFDIAG (26)ssm 0,0MFDIAG_1 (28)shrpd ret0,%r0,%sar,%r1MTDIAG_1 (1)STDIAG (26)ssm 0,0b,n perf_rdr_shift_in_W_leave;; RDR 27 read sequence;SFDIAG (27)ssm 0,0MFDIAG_1 (28)shrpd ret0,%r0,%sar,%r1MTDIAG_1 (1)STDIAG (27)ssm 0,0b,n perf_rdr_shift_in_W_leave;; RDR 28 read sequence;syncssm 0,0SFDIAG (28)ssm 0,0MFDIAG_1 (28)b,n perf_rdr_shift_in_W_leavessm 0,0nop;; RDR 29 read sequence;syncssm 0,0SFDIAG (29)ssm 0,0MFDIAG_1 (28)b,n perf_rdr_shift_in_W_leavessm 0,0nop;; RDR 30 read sequence;SFDIAG (30)ssm 0,0MFDIAG_1 (28)shrpd ret0,%r0,%sar,%r1MTDIAG_1 (1)STDIAG (30)ssm 0,0b,n perf_rdr_shift_in_W_leave;; RDR 31 read sequence;syncssm 0,0SFDIAG (31)ssm 0,0MFDIAG_1 (28)nopssm 0,0nop;; Fallthrough;perf_rdr_shift_in_W_leave:bve (%r2).exitMTDIAG_2 (24) ; restore DR2.procend;************************************************************************;* *;* Name: perf_rdr_shift_out_W *;* *;* Description: *;* This routine moves data to the RDR's. The double-word that *;* arg1 points to is loaded and moved into the staging register. *;* Then the STDIAG instruction for the RDR # in arg0 is called *;* to move the data to the RDR. *;* *;* Arguments: *;* arg0 = rdr number *;* arg1 = 64-bit value to write *;* %r24 - DR2 | DR2_SLOW_RET *;* %r23 - original DR2 value *;* *;* Returns: *;* None *;* *;* Register usage: *;* *;************************************************************************.export perf_rdr_shift_out_W,codeperf_rdr_shift_out_W:.proc.callinfo frame=0,NO_CALLS.entry;; NOTE: The PCX-W ERS states that DR2_SLOW_RET must be set before any; shifting is done, from or to, the remote diagnose registers.;depdi,z 1,DR2_SLOW_RET,1,%r24MFDIAG_2 (23)or %r24,%r23,%r24MTDIAG_2 (24) ; set DR2_SLOW_RETMTDIAG_1 (25) ; data to the staging registershladd arg0,2,%r0,%r1 ; %r1 = 4 * RDR numberblr %r1,%r0 ; branch to 8-instruction sequencenop;; RDR 0 write sequence;sync ; RDR 0 write sequencessm 0,0STDIAG (0)ssm 0,0b,n perf_rdr_shift_out_W_leavenopssm 0,0nop;; RDR 1 write sequence;syncssm 0,0STDIAG (1)ssm 0,0b,n perf_rdr_shift_out_W_leavenopssm 0,0nop;; RDR 2 write sequence;syncssm 0,0STDIAG (2)ssm 0,0b,n perf_rdr_shift_out_W_leavenopssm 0,0nop;; RDR 3 write sequence;syncssm 0,0STDIAG (3)ssm 0,0b,n perf_rdr_shift_out_W_leavenopssm 0,0nop;; RDR 4 write sequence;syncssm 0,0STDIAG (4)ssm 0,0b,n perf_rdr_shift_out_W_leavenopssm 0,0nop;; RDR 5 write sequence;syncssm 0,0STDIAG (5)ssm 0,0b,n perf_rdr_shift_out_W_leavenopssm 0,0nop;; RDR 6 write sequence;syncssm 0,0STDIAG (6)ssm 0,0b,n perf_rdr_shift_out_W_leavenopssm 0,0nop;; RDR 7 write sequence;syncssm 0,0STDIAG (7)ssm 0,0b,n perf_rdr_shift_out_W_leavenopssm 0,0nop;; RDR 8 write sequence;syncssm 0,0STDIAG (8)ssm 0,0b,n perf_rdr_shift_out_W_leavenopssm 0,0nop;; RDR 9 write sequence;syncssm 0,0STDIAG (9)ssm 0,0b,n perf_rdr_shift_out_W_leavenopssm 0,0nop;; RDR 10 write sequence;syncssm 0,0STDIAG (10)STDIAG (26)ssm 0,0b,n perf_rdr_shift_out_W_leavessm 0,0nop;; RDR 11 write sequence;syncssm 0,0STDIAG (11)STDIAG (27)ssm 0,0b,n perf_rdr_shift_out_W_leavessm 0,0nop;; RDR 12 write sequence;syncssm 0,0STDIAG (12)ssm 0,0b,n perf_rdr_shift_out_W_leavenopssm 0,0nop;; RDR 13 write sequence;syncssm 0,0STDIAG (13)ssm 0,0b,n perf_rdr_shift_out_W_leavenopssm 0,0nop;; RDR 14 write sequence;syncssm 0,0STDIAG (14)ssm 0,0b,n perf_rdr_shift_out_W_leavenopssm 0,0nop;; RDR 15 write sequence;syncssm 0,0STDIAG (15)ssm 0,0b,n perf_rdr_shift_out_W_leavenopssm 0,0nop;; RDR 16 write sequence;syncssm 0,0STDIAG (16)ssm 0,0b,n perf_rdr_shift_out_W_leavenopssm 0,0nop;; RDR 17 write sequence;syncssm 0,0STDIAG (17)ssm 0,0b,n perf_rdr_shift_out_W_leavenopssm 0,0nop;; RDR 18 write sequence;syncssm 0,0STDIAG (18)ssm 0,0b,n perf_rdr_shift_out_W_leavenopssm 0,0nop;; RDR 19 write sequence;syncssm 0,0STDIAG (19)ssm 0,0b,n perf_rdr_shift_out_W_leavenopssm 0,0nop;; RDR 20 write sequence;syncssm 0,0STDIAG (20)ssm 0,0b,n perf_rdr_shift_out_W_leavenopssm 0,0nop;; RDR 21 write sequence;syncssm 0,0STDIAG (21)ssm 0,0b,n perf_rdr_shift_out_W_leavenopssm 0,0nop;; RDR 22 write sequence;syncssm 0,0STDIAG (22)ssm 0,0b,n perf_rdr_shift_out_W_leavenopssm 0,0nop;; RDR 23 write sequence;syncssm 0,0STDIAG (23)ssm 0,0b,n perf_rdr_shift_out_W_leavenopssm 0,0nop;; RDR 24 write sequence;syncssm 0,0STDIAG (24)ssm 0,0b,n perf_rdr_shift_out_W_leavenopssm 0,0nop;; RDR 25 write sequence;syncssm 0,0STDIAG (25)ssm 0,0b,n perf_rdr_shift_out_W_leavenopssm 0,0nop;; RDR 26 write sequence;syncssm 0,0STDIAG (10)STDIAG (26)ssm 0,0b,n perf_rdr_shift_out_W_leavessm 0,0nop;; RDR 27 write sequence;syncssm 0,0STDIAG (11)STDIAG (27)ssm 0,0b,n perf_rdr_shift_out_W_leavessm 0,0nop;; RDR 28 write sequence;syncssm 0,0STDIAG (28)ssm 0,0b,n perf_rdr_shift_out_W_leavenopssm 0,0nop;; RDR 29 write sequence;syncssm 0,0STDIAG (29)ssm 0,0b,n perf_rdr_shift_out_W_leavenopssm 0,0nop;; RDR 30 write sequence;syncssm 0,0STDIAG (30)ssm 0,0b,n perf_rdr_shift_out_W_leavenopssm 0,0nop;; RDR 31 write sequence;syncssm 0,0STDIAG (31)ssm 0,0b,n perf_rdr_shift_out_W_leavenopssm 0,0nopperf_rdr_shift_out_W_leave:bve (%r2).exitMTDIAG_2 (23) ; restore DR2.procend;**************************** CHRIS ***********************************;************************************************************************;* *;* Name: rdr_shift_in_U *;* *;* Description: *;* This routine shifts data in from the RDR in arg0 and returns *;* the result in ret0. If the RDR is <= 64 bits in length, it *;* is shifted shifted backup immediately. This is to compensate *;* for RDR10 which has bits that preclude PDC stack operations *;* when they are in the wrong state. *;* *;* Arguments: *;* arg0 : rdr to be read *;* arg1 : bit length of rdr *;* *;* Returns: *;* ret0 = next 64 bits of rdr data from staging register *;* *;* Register usage: *;* arg0 : rdr to be read *;* arg1 : bit length of rdr *;* %r24 - original DR2 value *;* %r23 - DR2 | DR2_SLOW_RET *;* %r1 - scratch *;* *;************************************************************************.export perf_rdr_shift_in_U,codeperf_rdr_shift_in_U:.proc.callinfo frame=0,NO_CALLS.entry; read(shift in) the RDR.;; NOTE: The PCX-U ERS states that DR2_SLOW_RET must be set before any; shifting is done, from or to, remote diagnose registers.depdi,z 1,DR2_SLOW_RET,1,%r29MFDIAG_2 (24)or %r24,%r29,%r29MTDIAG_2 (29) ; set DR2_SLOW_RETnopnopnopnop;; Start of next 32-byte cacheline;nopnopnopextrd,u arg1,63,6,%r1mtsar %r1shladd arg0,2,%r0,%r1 ; %r1 = 4 * RDR numberblr %r1,%r0 ; branch to 8-instruction sequencenop;; Start of next 32-byte cacheline;SFDIAG (0) ; RDR 0 read sequencessm 0,0MFDIAG_1 (28)shrpd ret0,%r0,%sar,%r1MTDIAG_1 (1)STDIAG (0)ssm 0,0b,n perf_rdr_shift_in_U_leaveSFDIAG (1) ; RDR 1 read sequencessm 0,0MFDIAG_1 (28)shrpd ret0,%r0,%sar,%r1MTDIAG_1 (1)STDIAG (1)ssm 0,0b,n perf_rdr_shift_in_U_leavesync ; RDR 2 read sequencessm 0,0SFDIAG (4)ssm 0,0MFDIAG_1 (28)b,n perf_rdr_shift_in_U_leavessm 0,0nopsync ; RDR 3 read sequencessm 0,0SFDIAG (3)ssm 0,0MFDIAG_1 (28)b,n perf_rdr_shift_in_U_leavessm 0,0nopsync ; RDR 4 read sequencessm 0,0SFDIAG (4)ssm 0,0MFDIAG_1 (28)b,n perf_rdr_shift_in_U_leavessm 0,0nopsync ; RDR 5 read sequencessm 0,0SFDIAG (5)ssm 0,0MFDIAG_1 (28)b,n perf_rdr_shift_in_U_leavessm 0,0nopsync ; RDR 6 read sequencessm 0,0SFDIAG (6)ssm 0,0MFDIAG_1 (28)b,n perf_rdr_shift_in_U_leavessm 0,0nopsync ; RDR 7 read sequencessm 0,0SFDIAG (7)ssm 0,0MFDIAG_1 (28)b,n perf_rdr_shift_in_U_leavessm 0,0nopb,n perf_rdr_shift_in_U_leavenopnopnopnopnopnopnopSFDIAG (9) ; RDR 9 read sequencessm 0,0MFDIAG_1 (28)shrpd ret0,%r0,%sar,%r1MTDIAG_1 (1)STDIAG (9)ssm 0,0b,n perf_rdr_shift_in_U_leaveSFDIAG (10) ; RDR 10 read sequencessm 0,0MFDIAG_1 (28)shrpd ret0,%r0,%sar,%r1MTDIAG_1 (1)STDIAG (10)ssm 0,0b,n perf_rdr_shift_in_U_leaveSFDIAG (11) ; RDR 11 read sequencessm 0,0MFDIAG_1 (28)shrpd ret0,%r0,%sar,%r1MTDIAG_1 (1)STDIAG (11)ssm 0,0b,n perf_rdr_shift_in_U_leaveSFDIAG (12) ; RDR 12 read sequencessm 0,0MFDIAG_1 (28)shrpd ret0,%r0,%sar,%r1MTDIAG_1 (1)STDIAG (12)ssm 0,0b,n perf_rdr_shift_in_U_leaveSFDIAG (13) ; RDR 13 read sequencessm 0,0MFDIAG_1 (28)shrpd ret0,%r0,%sar,%r1MTDIAG_1 (1)STDIAG (13)ssm 0,0b,n perf_rdr_shift_in_U_leaveSFDIAG (14) ; RDR 14 read sequencessm 0,0MFDIAG_1 (28)shrpd ret0,%r0,%sar,%r1MTDIAG_1 (1)STDIAG (14)ssm 0,0b,n perf_rdr_shift_in_U_leaveSFDIAG (15) ; RDR 15 read sequencessm 0,0MFDIAG_1 (28)shrpd ret0,%r0,%sar,%r1MTDIAG_1 (1)STDIAG (15)ssm 0,0b,n perf_rdr_shift_in_U_leavesync ; RDR 16 read sequencessm 0,0SFDIAG (16)ssm 0,0MFDIAG_1 (28)b,n perf_rdr_shift_in_U_leavessm 0,0nopSFDIAG (17) ; RDR 17 read sequencessm 0,0MFDIAG_1 (28)shrpd ret0,%r0,%sar,%r1MTDIAG_1 (1)STDIAG (17)ssm 0,0b,n perf_rdr_shift_in_U_leaveSFDIAG (18) ; RDR 18 read sequencessm 0,0MFDIAG_1 (28)shrpd ret0,%r0,%sar,%r1MTDIAG_1 (1)STDIAG (18)ssm 0,0b,n perf_rdr_shift_in_U_leaveb,n perf_rdr_shift_in_U_leavenopnopnopnopnopnopnopsync ; RDR 20 read sequencessm 0,0SFDIAG (20)ssm 0,0MFDIAG_1 (28)b,n perf_rdr_shift_in_U_leavessm 0,0nopsync ; RDR 21 read sequencessm 0,0SFDIAG (21)ssm 0,0MFDIAG_1 (28)b,n perf_rdr_shift_in_U_leavessm 0,0nopsync ; RDR 22 read sequencessm 0,0SFDIAG (22)ssm 0,0MFDIAG_1 (28)b,n perf_rdr_shift_in_U_leavessm 0,0nopsync ; RDR 23 read sequencessm 0,0SFDIAG (23)ssm 0,0MFDIAG_1 (28)b,n perf_rdr_shift_in_U_leavessm 0,0nopsync ; RDR 24 read sequencessm 0,0SFDIAG (24)ssm 0,0MFDIAG_1 (28)b,n perf_rdr_shift_in_U_leavessm 0,0nopsync ; RDR 25 read sequencessm 0,0SFDIAG (25)ssm 0,0MFDIAG_1 (28)b,n perf_rdr_shift_in_U_leavessm 0,0nopSFDIAG (26) ; RDR 26 read sequencessm 0,0MFDIAG_1 (28)shrpd ret0,%r0,%sar,%r1MTDIAG_1 (1)STDIAG (26)ssm 0,0b,n perf_rdr_shift_in_U_leaveSFDIAG (27) ; RDR 27 read sequencessm 0,0MFDIAG_1 (28)shrpd ret0,%r0,%sar,%r1MTDIAG_1 (1)STDIAG (27)ssm 0,0b,n perf_rdr_shift_in_U_leavesync ; RDR 28 read sequencessm 0,0SFDIAG (28)ssm 0,0MFDIAG_1 (28)b,n perf_rdr_shift_in_U_leavessm 0,0nopb,n perf_rdr_shift_in_U_leavenopnopnopnopnopnopnopSFDIAG (30) ; RDR 30 read sequencessm 0,0MFDIAG_1 (28)shrpd ret0,%r0,%sar,%r1MTDIAG_1 (1)STDIAG (30)ssm 0,0b,n perf_rdr_shift_in_U_leaveSFDIAG (31) ; RDR 31 read sequencessm 0,0MFDIAG_1 (28)shrpd ret0,%r0,%sar,%r1MTDIAG_1 (1)STDIAG (31)ssm 0,0b,n perf_rdr_shift_in_U_leavenopperf_rdr_shift_in_U_leave:bve (%r2).exitMTDIAG_2 (24) ; restore DR2.procend;************************************************************************;* *;* Name: rdr_shift_out_U *;* *;* Description: *;* This routine moves data to the RDR's. The double-word that *;* arg1 points to is loaded and moved into the staging register. *;* Then the STDIAG instruction for the RDR # in arg0 is called *;* to move the data to the RDR. *;* *;* Arguments: *;* arg0 = rdr target *;* arg1 = buffer pointer *;* *;* Returns: *;* None *;* *;* Register usage: *;* arg0 = rdr target *;* arg1 = buffer pointer *;* %r24 - DR2 | DR2_SLOW_RET *;* %r23 - original DR2 value *;* *;************************************************************************.export perf_rdr_shift_out_U,codeperf_rdr_shift_out_U:.proc.callinfo frame=0,NO_CALLS.entry;; NOTE: The PCX-U ERS states that DR2_SLOW_RET must be set before any; shifting is done, from or to, the remote diagnose registers.;depdi,z 1,DR2_SLOW_RET,1,%r24MFDIAG_2 (23)or %r24,%r23,%r24MTDIAG_2 (24) ; set DR2_SLOW_RETMTDIAG_1 (25) ; data to the staging registershladd arg0,2,%r0,%r1 ; %r1 = 4 * RDR numberblr %r1,%r0 ; branch to 8-instruction sequencenop;; 32-byte cachline aligned;sync ; RDR 0 write sequencessm 0,0STDIAG (0)ssm 0,0b,n perf_rdr_shift_out_U_leavenopssm 0,0nopsync ; RDR 1 write sequencessm 0,0STDIAG (1)ssm 0,0b,n perf_rdr_shift_out_U_leavenopssm 0,0nopsync ; RDR 2 write sequencessm 0,0STDIAG (2)ssm 0,0b,n perf_rdr_shift_out_U_leavenopssm 0,0nopsync ; RDR 3 write sequencessm 0,0STDIAG (3)ssm 0,0b,n perf_rdr_shift_out_U_leavenopssm 0,0nopsync ; RDR 4 write sequencessm 0,0STDIAG (4)ssm 0,0b,n perf_rdr_shift_out_U_leavenopssm 0,0nopsync ; RDR 5 write sequencessm 0,0STDIAG (5)ssm 0,0b,n perf_rdr_shift_out_U_leavenopssm 0,0nopsync ; RDR 6 write sequencessm 0,0STDIAG (6)ssm 0,0b,n perf_rdr_shift_out_U_leavenopssm 0,0nopsync ; RDR 7 write sequencessm 0,0STDIAG (7)ssm 0,0b,n perf_rdr_shift_out_U_leavenopssm 0,0nopsync ; RDR 8 write sequencessm 0,0STDIAG (8)ssm 0,0b,n perf_rdr_shift_out_U_leavenopssm 0,0nopsync ; RDR 9 write sequencessm 0,0STDIAG (9)ssm 0,0b,n perf_rdr_shift_out_U_leavenopssm 0,0nopsync ; RDR 10 write sequencessm 0,0STDIAG (10)ssm 0,0b,n perf_rdr_shift_out_U_leavenopssm 0,0nopsync ; RDR 11 write sequencessm 0,0STDIAG (11)ssm 0,0b,n perf_rdr_shift_out_U_leavenopssm 0,0nopsync ; RDR 12 write sequencessm 0,0STDIAG (12)ssm 0,0b,n perf_rdr_shift_out_U_leavenopssm 0,0nopsync ; RDR 13 write sequencessm 0,0STDIAG (13)ssm 0,0b,n perf_rdr_shift_out_U_leavenopssm 0,0nopsync ; RDR 14 write sequencessm 0,0STDIAG (14)ssm 0,0b,n perf_rdr_shift_out_U_leavenopssm 0,0nopsync ; RDR 15 write sequencessm 0,0STDIAG (15)ssm 0,0b,n perf_rdr_shift_out_U_leavenopssm 0,0nopsync ; RDR 16 write sequencessm 0,0STDIAG (16)ssm 0,0b,n perf_rdr_shift_out_U_leavenopssm 0,0nopsync ; RDR 17 write sequencessm 0,0STDIAG (17)ssm 0,0b,n perf_rdr_shift_out_U_leavenopssm 0,0nopsync ; RDR 18 write sequencessm 0,0STDIAG (18)ssm 0,0b,n perf_rdr_shift_out_U_leavenopssm 0,0nopsync ; RDR 19 write sequencessm 0,0STDIAG (19)ssm 0,0b,n perf_rdr_shift_out_U_leavenopssm 0,0nopsync ; RDR 20 write sequencessm 0,0STDIAG (20)ssm 0,0b,n perf_rdr_shift_out_U_leavenopssm 0,0nopsync ; RDR 21 write sequencessm 0,0STDIAG (21)ssm 0,0b,n perf_rdr_shift_out_U_leavenopssm 0,0nopsync ; RDR 22 write sequencessm 0,0STDIAG (22)ssm 0,0b,n perf_rdr_shift_out_U_leavenopssm 0,0nopsync ; RDR 23 write sequencessm 0,0STDIAG (23)ssm 0,0b,n perf_rdr_shift_out_U_leavenopssm 0,0nopsync ; RDR 24 write sequencessm 0,0STDIAG (24)ssm 0,0b,n perf_rdr_shift_out_U_leavenopssm 0,0nopsync ; RDR 25 write sequencessm 0,0STDIAG (25)ssm 0,0b,n perf_rdr_shift_out_U_leavenopssm 0,0nopsync ; RDR 26 write sequencessm 0,0STDIAG (26)ssm 0,0b,n perf_rdr_shift_out_U_leavenopssm 0,0nopsync ; RDR 27 write sequencessm 0,0STDIAG (27)ssm 0,0b,n perf_rdr_shift_out_U_leavenopssm 0,0nopsync ; RDR 28 write sequencessm 0,0STDIAG (28)ssm 0,0b,n perf_rdr_shift_out_U_leavenopssm 0,0nopsync ; RDR 29 write sequencessm 0,0STDIAG (29)ssm 0,0b,n perf_rdr_shift_out_U_leavenopssm 0,0nopsync ; RDR 30 write sequencessm 0,0STDIAG (30)ssm 0,0b,n perf_rdr_shift_out_U_leavenopssm 0,0nopsync ; RDR 31 write sequencessm 0,0STDIAG (31)ssm 0,0b,n perf_rdr_shift_out_U_leavenopssm 0,0nopperf_rdr_shift_out_U_leave:bve (%r2).exitMTDIAG_2 (23) ; restore DR2.procend
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