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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [drivers/] [scsi/] [aic7xxx/] [aic79xx.reg] - Rev 1765
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/** Aic79xx register and scratch ram definitions.** Copyright (c) 1994-2001 Justin T. Gibbs.* Copyright (c) 2000-2002 Adaptec Inc.* All rights reserved.** Redistribution and use in source and binary forms, with or without* modification, are permitted provided that the following conditions* are met:* 1. Redistributions of source code must retain the above copyright* notice, this list of conditions, and the following disclaimer,* without modification.* 2. Redistributions in binary form must reproduce at minimum a disclaimer* substantially similar to the "NO WARRANTY" disclaimer below* ("Disclaimer") and any redistribution must be conditioned upon* including a substantially similar Disclaimer requirement for further* binary redistribution.* 3. Neither the names of the above-listed copyright holders nor the names* of any contributors may be used to endorse or promote products derived* from this software without specific prior written permission.** Alternatively, this software may be distributed under the terms of the* GNU General Public License ("GPL") version 2 as published by the Free* Software Foundation.** NO WARRANTY* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE* POSSIBILITY OF SUCH DAMAGES.** $FreeBSD$*/VERSION = "$Id: aic79xx.reg,v 1.1.1.1 2004-04-15 02:16:10 phoenix Exp $"/** This file is processed by the aic7xxx_asm utility for use in assembling* firmware for the aic79xx family of SCSI host adapters as well as to generate* a C header file for use in the kernel portion of the Aic79xx driver.*//* Register window Modes */#define M_DFF0 0#define M_DFF1 1#define M_CCHAN 2#define M_SCSI 3#define M_CFG 4#define M_DST_SHIFT 4#define MK_MODE(src, dst) ((src) | ((dst) << M_DST_SHIFT))#define SET_MODE(src, dst) \SET_SRC_MODE src; \SET_DST_MODE dst; \if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \mvi MK_MODE(src, dst) call set_mode_work_around; \} else { \mvi MODE_PTR, MK_MODE(src, dst); \}#define TOGGLE_DFF_MODE \if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \call toggle_dff_mode_work_around; \} else { \xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1); \}#define RESTORE_MODE(mode) \if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \mov mode call set_mode_work_around; \} else { \mov MODE_PTR, mode; \}#define SET_SEQINTCODE(code) \if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { \mvi code call set_seqint_work_around; \} else { \mvi SEQINTCODE, code; \}/** Mode Pointer* Controls which of the 5, 512byte, address spaces should be used* as the source and destination of any register accesses in our* register window.*/register MODE_PTR {address 0x000access_mode RWfield DST_MODE 0x70field SRC_MODE 0x07mode_pointer}const SRC_MODE_SHIFT 0const DST_MODE_SHIFT 4/** Host Interrupt Status*/register INTSTAT {address 0x001access_mode RWfield HWERRINT 0x80field BRKADRINT 0x40field SWTMINT 0x20field PCIINT 0x10field SCSIINT 0x08field SEQINT 0x04field CMDCMPLT 0x02field SPLTINT 0x01mask INT_PEND 0xFF}/** Sequencer Interrupt Code*/register SEQINTCODE {address 0x002access_mode RWfield {NO_SEQINT, /* No seqint pending. */BAD_PHASE, /* unknown scsi bus phase */SEND_REJECT, /* sending a message reject */PROTO_VIOLATION, /* Protocol Violation */NO_MATCH, /* no cmd match for reconnect */IGN_WIDE_RES, /* Complex IGN Wide Res Msg */PDATA_REINIT, /** Returned to data phase* that requires data* transfer pointers to be* recalculated from the* transfer residual.*/HOST_MSG_LOOP, /** The bus is ready for the* host to perform another* message transaction. This* mechanism is used for things* like sync/wide negotiation* that require a kernel based* message state engine.*/BAD_STATUS, /* Bad status from target */DATA_OVERRUN, /** Target attempted to write* beyond the bounds of its* command.*/MKMSG_FAILED, /** Target completed command* without honoring our ATN* request to issue a message.*/MISSED_BUSFREE, /** The sequencer never saw* the bus go free after* either a command complete* or disconnect message.*/DUMP_CARD_STATE,ILLEGAL_PHASE,INVALID_SEQINT,CFG4ISTAT_INTR,STATUS_OVERRUN,CFG4OVERRUN,ENTERING_NONPACK,TASKMGMT_FUNC_COMPLETE, /** Task management function* request completed with* an expected busfree.*/TASKMGMT_CMD_CMPLT_OKAY, /** A command with a non-zero* task management function* has completed via the normal* command completion method* for commands with a zero* task management function.* This happens when an attempt* to abort a command loses* the race for the command to* complete normally.*/TRACEPOINT0,TRACEPOINT1,TRACEPOINT2,TRACEPOINT3,SAW_HWERR,BAD_SCB_STATUS}}/** Clear Host Interrupt*/register CLRINT {address 0x003access_mode WOfield CLRHWERRINT 0x80 /* Rev B or greater */field CLRBRKADRINT 0x40field CLRSWTMINT 0x20field CLRPCIINT 0x10field CLRSCSIINT 0x08field CLRSEQINT 0x04field CLRCMDINT 0x02field CLRSPLTINT 0x01}/** Error Register*/register ERROR {address 0x004access_mode ROfield CIOPARERR 0x80field CIOACCESFAIL 0x40 /* Rev B or greater */field MPARERR 0x20field DPARERR 0x10field SQPARERR 0x08field ILLOPCODE 0x04field DSCTMOUT 0x02}/** Clear Error*/register CLRERR {address 0x004access_mode WOfield CLRCIOPARERR 0x80field CLRCIOACCESFAIL 0x40 /* Rev B or greater */field CLRMPARERR 0x20field CLRDPARERR 0x10field CLRSQPARERR 0x08field CLRILLOPCODE 0x04field CLRDSCTMOUT 0x02}/** Host Control Register* Overall host control of the device.*/register HCNTRL {address 0x005access_mode RWfield SEQ_RESET 0x80 /* Rev B or greater */field POWRDN 0x40field SWINT 0x10field SWTIMER_START_B 0x08 /* Rev B or greater */field PAUSE 0x04field INTEN 0x02field CHIPRST 0x01field CHIPRSTACK 0x01}/** Host New SCB Queue Offset*/register HNSCB_QOFF {address 0x006access_mode RWsize 2}/** Host Empty SCB Queue Offset*/register HESCB_QOFF {address 0x008access_mode RW}/** Host Mailbox*/register HS_MAILBOX {address 0x00Baccess_mode RWmask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */mask ENINT_COALESCE 0x40 /* Perform interrupt coalescing */}/** Sequencer Interupt Status*/register SEQINTSTAT {address 0x00Caccess_mode ROfield SEQ_SWTMRTO 0x10field SEQ_SEQINT 0x08field SEQ_SCSIINT 0x04field SEQ_PCIINT 0x02field SEQ_SPLTINT 0x01}/** Clear SEQ Interrupt*/register CLRSEQINTSTAT {address 0x00Caccess_mode WOfield CLRSEQ_SWTMRTO 0x10field CLRSEQ_SEQINT 0x08field CLRSEQ_SCSIINT 0x04field CLRSEQ_PCIINT 0x02field CLRSEQ_SPLTINT 0x01}/** Software Timer*/register SWTIMER {address 0x00Eaccess_mode RWsize 2}/** SEQ New SCB Queue Offset*/register SNSCB_QOFF {address 0x010access_mode RWsize 2modes M_CCHAN}/** SEQ Empty SCB Queue Offset*/register SESCB_QOFF {address 0x012access_mode RWmodes M_CCHAN}/** SEQ Done SCB Queue Offset*/register SDSCB_QOFF {address 0x014access_mode RWmodes M_CCHANsize 2}/** Queue Offset Control & Status*/register QOFF_CTLSTA {address 0x016access_mode RWmodes M_CCHANfield EMPTY_SCB_AVAIL 0x80field NEW_SCB_AVAIL 0x40field SDSCB_ROLLOVR 0x20field HS_MAILBOX_ACT 0x10field SCB_QSIZE 0x0F {SCB_QSIZE_4,SCB_QSIZE_8,SCB_QSIZE_16,SCB_QSIZE_32,SCB_QSIZE_64,SCB_QSIZE_128,SCB_QSIZE_256,SCB_QSIZE_512,SCB_QSIZE_1024,SCB_QSIZE_2048,SCB_QSIZE_4096,SCB_QSIZE_8192,SCB_QSIZE_16384}}/** Interrupt Control*/register INTCTL {address 0x018access_mode RWfield SWTMINTMASK 0x80field SWTMINTEN 0x40field SWTIMER_START 0x20field AUTOCLRCMDINT 0x10field PCIINTEN 0x08field SCSIINTEN 0x04field SEQINTEN 0x02field SPLTINTEN 0x01}/** Data FIFO Control*/register DFCNTRL {address 0x019access_mode RWmodes M_DFF0, M_DFF1field PRELOADEN 0x80field SCSIENWRDIS 0x40 /* Rev B only. */field SCSIEN 0x20field SCSIENACK 0x20field HDMAEN 0x08field HDMAENACK 0x08field DIRECTION 0x04field DIRECTIONACK 0x04field FIFOFLUSH 0x02field FIFOFLUSHACK 0x02field DIRECTIONEN 0x01}/** Device Space Command 0*/register DSCOMMAND0 {address 0x019access_mode RWmodes M_CFGfield CACHETHEN 0x80 /* Cache Threshold enable */field DPARCKEN 0x40 /* Data Parity Check Enable */field MPARCKEN 0x20 /* Memory Parity Check Enable */field EXTREQLCK 0x10 /* External Request Lock */field DISABLE_TWATE 0x02 /* Rev B or greater */field CIOPARCKEN 0x01 /* Internal bus parity error enable */}/** Data FIFO Status*/register DFSTATUS {address 0x01Aaccess_mode ROmodes M_DFF0, M_DFF1field PRELOAD_AVAIL 0x80field PKT_PRELOAD_AVAIL 0x40field MREQPEND 0x10field HDONE 0x08field DFTHRESH 0x04field FIFOFULL 0x02field FIFOEMP 0x01}/** S/G Cache Pointer*/register SG_CACHE_PRE {address 0x01Baccess_mode WOmodes M_DFF0, M_DFF1field SG_ADDR_MASK 0xf8field ODD_SEG 0x04field LAST_SEG 0x02}register SG_CACHE_SHADOW {address 0x01Baccess_mode ROmodes M_DFF0, M_DFF1field SG_ADDR_MASK 0xf8field ODD_SEG 0x04field LAST_SEG 0x02field LAST_SEG_DONE 0x01}/** Arbiter Control*/register ARBCTL {address 0x01Baccess_mode RWmodes M_CFGfield RESET_HARB 0x80field RETRY_SWEN 0x08field USE_TIME 0x07}/** Data Channel Host Address*/register HADDR {address 0x070access_mode RWsize 8modes M_DFF0, M_DFF1}/** Host Overlay DMA Address*/register HODMAADR {address 0x070access_mode RWsize 8modes M_SCSI}/** PCI PLL Delay.*/register PLLDELAY {address 0x070access_mode RWsize 1modes M_CFGfield SPLIT_DROP_REQ 0x80}/** Data Channel Host Count*/register HCNT {address 0x078access_mode RWsize 3modes M_DFF0, M_DFF1}/** Host Overlay DMA Count*/register HODMACNT {address 0x078access_mode RWsize 2modes M_SCSI}/** Host Overlay DMA Enable*/register HODMAEN {address 0x07Aaccess_mode RWmodes M_SCSI}/** Scatter/Gather Host Address*/register SGHADDR {address 0x07Caccess_mode RWsize 8modes M_DFF0, M_DFF1}/** SCB Host Address*/register SCBHADDR {address 0x07Caccess_mode RWsize 8modes M_CCHAN}/** Scatter/Gather Host Count*/register SGHCNT {address 0x084access_mode RWmodes M_DFF0, M_DFF1}/** SCB Host Count*/register SCBHCNT {address 0x084access_mode RWmodes M_CCHAN}/** Data FIFO Threshold*/register DFF_THRSH {address 0x088access_mode RWmodes M_CFGfield WR_DFTHRSH 0x70 {WR_DFTHRSH_MIN,WR_DFTHRSH_25,WR_DFTHRSH_50,WR_DFTHRSH_63,WR_DFTHRSH_75,WR_DFTHRSH_85,WR_DFTHRSH_90,WR_DFTHRSH_MAX}field RD_DFTHRSH 0x07 {RD_DFTHRSH_MIN,RD_DFTHRSH_25,RD_DFTHRSH_50,RD_DFTHRSH_63,RD_DFTHRSH_75,RD_DFTHRSH_85,RD_DFTHRSH_90,RD_DFTHRSH_MAX}}/** ROM Address*/register ROMADDR {address 0x08Aaccess_mode RWsize 3}/** ROM Control*/register ROMCNTRL {address 0x08Daccess_mode RWfield ROMOP 0xE0field ROMSPD 0x18field REPEAT 0x02field RDY 0x01}/** ROM Data*/register ROMDATA {address 0x08Eaccess_mode RW}/** Data Channel Receive Message 0*/register DCHRXMSG0 {address 0x090access_mode ROmodes M_DFF0, M_DFF1field CDNUM 0xF8field CFNUM 0x07}/** CMC Recieve Message 0*/register CMCRXMSG0 {address 0x090access_mode ROmodes M_CCHANfield CDNUM 0xF8field CFNUM 0x07}/** Overlay Recieve Message 0*/register OVLYRXMSG0 {address 0x090access_mode ROmodes M_SCSIfield CDNUM 0xF8field CFNUM 0x07}/** Relaxed Order Enable*/register ROENABLE {address 0x090access_mode RWmodes M_CFGfield MSIROEN 0x20field OVLYROEN 0x10field CMCROEN 0x08field SGROEN 0x04field DCH1ROEN 0x02field DCH0ROEN 0x01}/** Data Channel Receive Message 1*/register DCHRXMSG1 {address 0x091access_mode ROmodes M_DFF0, M_DFF1field CBNUM 0xFF}/** CMC Recieve Message 1*/register CMCRXMSG1 {address 0x091access_mode ROmodes M_CCHANfield CBNUM 0xFF}/** Overlay Recieve Message 1*/register OVLYRXMSG1 {address 0x091access_mode ROmodes M_SCSIfield CBNUM 0xFF}/** No Snoop Enable*/register NSENABLE {address 0x091access_mode RWmodes M_CFGfield MSINSEN 0x20field OVLYNSEN 0x10field CMCNSEN 0x08field SGNSEN 0x04field DCH1NSEN 0x02field DCH0NSEN 0x01}/** Data Channel Receive Message 2*/register DCHRXMSG2 {address 0x092access_mode ROmodes M_DFF0, M_DFF1field MINDEX 0xFF}/** CMC Recieve Message 2*/register CMCRXMSG2 {address 0x092access_mode ROmodes M_CCHANfield MINDEX 0xFF}/** Overlay Recieve Message 2*/register OVLYRXMSG2 {address 0x092access_mode ROmodes M_SCSIfield MINDEX 0xFF}/** Outstanding Split Transactions*/register OST {address 0x092access_mode RWmodes M_CFG}/** Data Channel Receive Message 3*/register DCHRXMSG3 {address 0x093access_mode ROmodes M_DFF0, M_DFF1field MCLASS 0x0F}/** CMC Recieve Message 3*/register CMCRXMSG3 {address 0x093access_mode ROmodes M_CCHANfield MCLASS 0x0F}/** Overlay Recieve Message 3*/register OVLYRXMSG3 {address 0x093access_mode ROmodes M_SCSIfield MCLASS 0x0F}/** PCI-X Control*/register PCIXCTL {address 0x093access_mode RWmodes M_CFGfield SERRPULSE 0x80field UNEXPSCIEN 0x20field SPLTSMADIS 0x10field SPLTSTADIS 0x08field SRSPDPEEN 0x04field TSCSERREN 0x02field CMPABCDIS 0x01}/** CMC Sequencer Byte Count*/register CMCSEQBCNT {address 0x094access_mode ROmodes M_CCHAN}/** Overlay Sequencer Byte Count*/register OVLYSEQBCNT {address 0x094access_mode ROmodes M_SCSI}/** Data Channel Sequencer Byte Count*/register DCHSEQBCNT {address 0x094access_mode ROsize 2modes M_DFF0, M_DFF1}/** Data Channel Split Status 0*/register DCHSPLTSTAT0 {address 0x096access_mode RWmodes M_DFF0, M_DFF1field STAETERM 0x80field SCBCERR 0x40field SCADERR 0x20field SCDATBUCKET 0x10field CNTNOTCMPLT 0x08field RXOVRUN 0x04field RXSCEMSG 0x02field RXSPLTRSP 0x01}/** CMC Split Status 0*/register CMCSPLTSTAT0 {address 0x096access_mode RWmodes M_CCHANfield STAETERM 0x80field SCBCERR 0x40field SCADERR 0x20field SCDATBUCKET 0x10field CNTNOTCMPLT 0x08field RXOVRUN 0x04field RXSCEMSG 0x02field RXSPLTRSP 0x01}/** Overlay Split Status 0*/register OVLYSPLTSTAT0 {address 0x096access_mode RWmodes M_SCSIfield STAETERM 0x80field SCBCERR 0x40field SCADERR 0x20field SCDATBUCKET 0x10field CNTNOTCMPLT 0x08field RXOVRUN 0x04field RXSCEMSG 0x02field RXSPLTRSP 0x01}/** Data Channel Split Status 1*/register DCHSPLTSTAT1 {address 0x097access_mode RWmodes M_DFF0, M_DFF1field RXDATABUCKET 0x01}/** CMC Split Status 1*/register CMCSPLTSTAT1 {address 0x097access_mode RWmodes M_CCHANfield RXDATABUCKET 0x01}/** Overlay Split Status 1*/register OVLYSPLTSTAT1 {address 0x097access_mode RWmodes M_SCSIfield RXDATABUCKET 0x01}/** S/G Receive Message 0*/register SGRXMSG0 {address 0x098access_mode ROmodes M_DFF0, M_DFF1field CDNUM 0xF8field CFNUM 0x07}/** S/G Receive Message 1*/register SGRXMSG1 {address 0x099access_mode ROmodes M_DFF0, M_DFF1field CBNUM 0xFF}/** S/G Receive Message 2*/register SGRXMSG2 {address 0x09Aaccess_mode ROmodes M_DFF0, M_DFF1field MINDEX 0xFF}/** S/G Receive Message 3*/register SGRXMSG3 {address 0x09Baccess_mode ROmodes M_DFF0, M_DFF1field MCLASS 0x0F}/** Slave Split Out Address 0*/register SLVSPLTOUTADR0 {address 0x098access_mode ROmodes M_SCSIfield LOWER_ADDR 0x7F}/** Slave Split Out Address 1*/register SLVSPLTOUTADR1 {address 0x099access_mode ROmodes M_SCSIfield REQ_DNUM 0xF8field REQ_FNUM 0x07}/** Slave Split Out Address 2*/register SLVSPLTOUTADR2 {address 0x09Aaccess_mode ROmodes M_SCSIfield REQ_BNUM 0xFF}/** Slave Split Out Address 3*/register SLVSPLTOUTADR3 {address 0x09Baccess_mode ROmodes M_SCSIfield RLXORD 020field TAG_NUM 0x1F}/** SG Sequencer Byte Count*/register SGSEQBCNT {address 0x09Caccess_mode ROmodes M_DFF0, M_DFF1}/** Slave Split Out Attribute 0*/register SLVSPLTOUTATTR0 {address 0x09Caccess_mode ROmodes M_SCSIfield LOWER_BCNT 0xFF}/** Slave Split Out Attribute 1*/register SLVSPLTOUTATTR1 {address 0x09Daccess_mode ROmodes M_SCSIfield CMPLT_DNUM 0xF8field CMPLT_FNUM 0x07}/** Slave Split Out Attribute 2*/register SLVSPLTOUTATTR2 {address 0x09Eaccess_mode ROsize 2modes M_SCSIfield CMPLT_BNUM 0xFF}/** S/G Split Status 0*/register SGSPLTSTAT0 {address 0x09Eaccess_mode RWmodes M_DFF0, M_DFF1field STAETERM 0x80field SCBCERR 0x40field SCADERR 0x20field SCDATBUCKET 0x10field CNTNOTCMPLT 0x08field RXOVRUN 0x04field RXSCEMSG 0x02field RXSPLTRSP 0x01}/** S/G Split Status 1*/register SGSPLTSTAT1 {address 0x09Faccess_mode RWmodes M_DFF0, M_DFF1field RXDATABUCKET 0x01}/** Special Function*/register SFUNCT {address 0x09faccess_mode RWmodes M_CFGfield TEST_GROUP 0xF0field TEST_NUM 0x0F}/** Data FIFO 0 PCI Status*/register DF0PCISTAT {address 0x0A0access_mode RWmodes M_CFGfield DPE 0x80field SSE 0x40field RMA 0x20field RTA 0x10field SCAAPERR 0x08field RDPERR 0x04field TWATERR 0x02field DPR 0x01}/** Data FIFO 1 PCI Status*/register DF1PCISTAT {address 0x0A1access_mode RWmodes M_CFGfield DPE 0x80field SSE 0x40field RMA 0x20field RTA 0x10field SCAAPERR 0x08field RDPERR 0x04field TWATERR 0x02field DPR 0x01}/** S/G PCI Status*/register SGPCISTAT {address 0x0A2access_mode RWmodes M_CFGfield DPE 0x80field SSE 0x40field RMA 0x20field RTA 0x10field SCAAPERR 0x08field RDPERR 0x04field DPR 0x01}/** CMC PCI Status*/register CMCPCISTAT {address 0x0A3access_mode RWmodes M_CFGfield DPE 0x80field SSE 0x40field RMA 0x20field RTA 0x10field SCAAPERR 0x08field RDPERR 0x04field TWATERR 0x02field DPR 0x01}/** Overlay PCI Status*/register OVLYPCISTAT {address 0x0A4access_mode RWmodes M_CFGfield DPE 0x80field SSE 0x40field RMA 0x20field RTA 0x10field SCAAPERR 0x08field RDPERR 0x04field DPR 0x01}/** PCI Status for MSI Master DMA Transfer*/register MSIPCISTAT {address 0x0A6access_mode RWmodes M_CFGfield SSE 0x40field RMA 0x20field RTA 0x10field CLRPENDMSI 0x08field TWATERR 0x02field DPR 0x01}/** PCI Status for Target*/register TARGPCISTAT {address 0x0A7access_mode RWmodes M_CFGfield DPE 0x80field SSE 0x40field STA 0x08field TWATERR 0x02}/** LQ Packet In* The last LQ Packet recieved*/register LQIN {address 0x020access_mode RWsize 20modes M_DFF0, M_DFF1, M_SCSI}/** SCB Type Pointer* SCB offset for Target Mode SCB type information*/register TYPEPTR {address 0x020access_mode RWmodes M_CFG}/** Queue Tag Pointer* SCB offset to the Two Byte tag identifier used for target mode.*/register TAGPTR {address 0x021access_mode RWmodes M_CFG}/** Logical Unit Number Pointer* SCB offset to the LSB (little endian) of the lun field.*/register LUNPTR {address 0x022access_mode RWmodes M_CFG}/** Data Length Pointer* SCB offset for the 4 byte data length field in target mode.*/register DATALENPTR {address 0x023access_mode RWmodes M_CFG}/** Status Length Pointer* SCB offset to the two byte status field in target SCBs.*/register STATLENPTR {address 0x024access_mode RWmodes M_CFG}/** Command Length Pointer* Scb offset for the CDB length field in initiator SCBs.*/register CMDLENPTR {address 0x025access_mode RWmodes M_CFG}/** Task Attribute Pointer* Scb offset for the byte field specifying the attribute byte* to be used in command packets.*/register ATTRPTR {address 0x026access_mode RWmodes M_CFG}/** Task Management Flags Pointer* Scb offset for the byte field specifying the attribute flags* byte to be used in command packets.*/register FLAGPTR {address 0x027access_mode RWmodes M_CFG}/** Command Pointer* Scb offset for the first byte in the CDB for initiator SCBs.*/register CMDPTR {address 0x028access_mode RWmodes M_CFG}/** Queue Next Pointer* Scb offset for the 2 byte "next scb link".*/register QNEXTPTR {address 0x029access_mode RWmodes M_CFG}/** SCSI ID Pointer* Scb offset to the value to place in the SCSIID register* during target mode connections.*/register IDPTR {address 0x02Aaccess_mode RWmodes M_CFG}/** Command Aborted Byte Pointer* Offset to the SCB flags field that includes the* "SCB aborted" status bit.*/register ABRTBYTEPTR {address 0x02Baccess_mode RWmodes M_CFG}/** Command Aborted Bit Pointer* Bit offset in the SCB flags field for "SCB aborted" status.*/register ABRTBITPTR {address 0x02Caccess_mode RWmodes M_CFG}/** Rev B or greater.*/register MAXCMDBYTES {address 0x02Daccess_mode RWmodes M_CFG}/** Rev B or greater.*/register MAXCMD2RCV {address 0x02Eaccess_mode RWmodes M_CFG}/** Rev B or greater.*/register SHORTTHRESH {address 0x02Faccess_mode RWmodes M_CFG}/** Logical Unit Number Length* The length, in bytes, of the SCB lun field.*/register LUNLEN {address 0x030access_mode RWmodes M_CFGmask ILUNLEN 0x0Fmask TLUNLEN 0xF0}const LUNLEN_SINGLE_LEVEL_LUN 0xF/** CDB Limit* The size, in bytes, of the embedded CDB field in initator SCBs.*/register CDBLIMIT {address 0x031access_mode RWmodes M_CFG}/** Maximum Commands* The maximum number of commands to issue during a* single packetized connection.*/register MAXCMD {address 0x032access_mode RWmodes M_CFG}/** Maximum Command Counter* The number of commands already sent during this connection*/register MAXCMDCNT {address 0x033access_mode RWmodes M_CFG}/** LQ Packet Reserved Bytes* The bytes to be sent in the currently reserved fileds* of all LQ packets.*/register LQRSVD01 {address 0x034access_mode RWmodes M_SCSI}register LQRSVD16 {address 0x035access_mode RWmodes M_SCSI}register LQRSVD17 {address 0x036access_mode RWmodes M_SCSI}/** Command Reserved 0* The byte to be sent for the reserved byte 0 of* outgoing command packets.*/register CMDRSVD0 {address 0x037access_mode RWmodes M_CFG}/** LQ Manager Control 0*/register LQCTL0 {address 0x038access_mode RWmodes M_CFGfield LQITARGCLT 0xC0field LQIINITGCLT 0x30field LQ0TARGCLT 0x0Cfield LQ0INITGCLT 0x03}/** LQ Manager Control 1*/register LQCTL1 {address 0x038access_mode RWmodes M_DFF0, M_DFF1, M_SCSIfield PCI2PCI 0x04field SINGLECMD 0x02field ABORTPENDING 0x01}/** LQ Manager Control 2*/register LQCTL2 {address 0x039access_mode RWmodes M_DFF0, M_DFF1, M_SCSIfield LQIRETRY 0x80field LQICONTINUE 0x40field LQITOIDLE 0x20field LQIPAUSE 0x10field LQORETRY 0x08field LQOCONTINUE 0x04field LQOTOIDLE 0x02field LQOPAUSE 0x01}/** SCSI RAM BIST0*/register SCSBIST0 {address 0x039access_mode RWmodes M_CFGfield GSBISTERR 0x40field GSBISTDONE 0x20field GSBISTRUN 0x10field OSBISTERR 0x04field OSBISTDONE 0x02field OSBISTRUN 0x01}/** SCSI Sequence Control0*/register SCSISEQ0 {address 0x03Aaccess_mode RWmodes M_DFF0, M_DFF1, M_SCSIfield TEMODEO 0x80field ENSELO 0x40field ENARBO 0x20field FORCEBUSFREE 0x10field SCSIRSTO 0x01}/** SCSI RAM BIST 1*/register SCSBIST1 {address 0x03Aaccess_mode RWmodes M_CFGfield NTBISTERR 0x04field NTBISTDONE 0x02field NTBISTRUN 0x01}/** SCSI Sequence Control 1*/register SCSISEQ1 {address 0x03Baccess_mode RWmodes M_DFF0, M_DFF1, M_SCSIfield MANUALCTL 0x40field ENSELI 0x20field ENRSELI 0x10field MANUALP 0x0Cfield ENAUTOATNP 0x02field ALTSTIM 0x01}/** SCSI Transfer Control 0*/register SXFRCTL0 {address 0x03Caccess_mode RWmodes M_SCSIfield DFON 0x80field DFPEXP 0x40field BIOSCANCELEN 0x10field SPIOEN 0x08}/** SCSI Transfer Control 1*/register SXFRCTL1 {address 0x03Daccess_mode RWmodes M_SCSIfield BITBUCKET 0x80field ENSACHK 0x40field ENSPCHK 0x20field STIMESEL 0x18field ENSTIMER 0x04field ACTNEGEN 0x02field STPWEN 0x01}/** SCSI Transfer Control 2*/register SXFRCTL2 {address 0x03Eaccess_mode RWmodes M_SCSIfield AUTORSTDIS 0x10field CMDDMAEN 0x08field ASU 0x07}/** SCSI Bus Initiator IDs* Bitmask of observed initiators on the bus.*/register BUSINITID {address 0x03Caccess_mode RWmodes M_CFGsize 2}/** Data Length Counters* Packet byte counter.*/register DLCOUNT {address 0x03Caccess_mode RWmodes M_DFF0, M_DFF1size 3}/** Data FIFO Status*/register DFFSTAT {address 0x03Faccess_mode RWmodes M_SCSIfield FIFO1FREE 0x20field FIFO0FREE 0x10/** On the B, this enum only works* in the read direction. For writes,* you must use the B version of the* CURRFIFO_0 definition which is defined* as a constant outside of this register* definition to avoid confusing the* register pretty printing code.*/enum CURRFIFO 0x03 {CURRFIFO_0,CURRFIFO_1,CURRFIFO_NONE 0x3}}const B_CURRFIFO_0 0x2/** SCSI Bus Target IDs* Bitmask of observed targets on the bus.*/register BUSTARGID {address 0x03Eaccess_mode RWmodes M_CFGsize 2}/** SCSI Control Signal Out*/register SCSISIGO {address 0x040access_mode RWmodes M_DFF0, M_DFF1, M_SCSIfield CDO 0x80field IOO 0x40field MSGO 0x20field ATNO 0x10field SELO 0x08field BSYO 0x04field REQO 0x02field ACKO 0x01/** Possible phases to write into SCSISIG0*/enum PHASE_MASK CDO|IOO|MSGO {P_DATAOUT 0x0,P_DATAIN IOO,P_DATAOUT_DT P_DATAOUT|MSGO,P_DATAIN_DT P_DATAIN|MSGO,P_COMMAND CDO,P_MESGOUT CDO|MSGO,P_STATUS CDO|IOO,P_MESGIN CDO|IOO|MSGO}}register SCSISIGI {address 0x041access_mode ROmodes M_DFF0, M_DFF1, M_SCSIfield CDI 0x80field IOI 0x40field MSGI 0x20field ATNI 0x10field SELI 0x08field BSYI 0x04field REQI 0x02field ACKI 0x01/** Possible phases in SCSISIGI*/enum PHASE_MASK CDO|IOO|MSGO {P_DATAOUT 0x0,P_DATAIN IOO,P_DATAOUT_DT P_DATAOUT|MSGO,P_DATAIN_DT P_DATAIN|MSGO,P_COMMAND CDO,P_MESGOUT CDO|MSGO,P_STATUS CDO|IOO,P_MESGIN CDO|IOO|MSGO}}/** Multiple Target IDs* Bitmask of ids to respond as a target.*/register MULTARGID {address 0x040access_mode RWmodes M_CFGsize 2}/** SCSI Phase*/register SCSIPHASE {address 0x042access_mode ROmodes M_DFF0, M_DFF1, M_SCSIfield STATUS_PHASE 0x20field COMMAND_PHASE 0x10field MSG_IN_PHASE 0x08field MSG_OUT_PHASE 0x04field DATA_PHASE_MASK 0x03 {DATA_OUT_PHASE 0x01,DATA_IN_PHASE 0x02}}/** SCSI Data 0 Image*/register SCSIDAT0_IMG {address 0x043access_mode RWmodes M_DFF0, M_DFF1, M_SCSI}/** SCSI Latched Data*/register SCSIDAT {address 0x044access_mode RWmodes M_DFF0, M_DFF1, M_SCSIsize 2}/** SCSI Data Bus*/register SCSIBUS {address 0x046access_mode RWmodes M_DFF0, M_DFF1, M_SCSIsize 2}/** Target ID In*/register TARGIDIN {address 0x048access_mode ROmodes M_DFF0, M_DFF1, M_SCSIfield CLKOUT 0x80field TARGID 0x0F}/** Selection/Reselection ID* Upper four bits are the device id. The ONEBIT is set when the re/selecting* device did not set its own ID.*/register SELID {address 0x049access_mode RWmodes M_DFF0, M_DFF1, M_SCSIfield SELID_MASK 0xf0field ONEBIT 0x08}/** SCSI Block Control* Controls Bus type and channel selection. SELWIDE allows for the* coexistence of 8bit and 16bit devices on a wide bus.*/register SBLKCTL {address 0x04Aaccess_mode RWmodes M_DFF0, M_DFF1, M_SCSIfield DIAGLEDEN 0x80field DIAGLEDON 0x40field ENAB40 0x08 /* LVD transceiver active */field ENAB20 0x04 /* SE/HVD transceiver active */field SELWIDE 0x02}/** Option Mode*/register OPTIONMODE {address 0x04Aaccess_mode RWmodes M_CFGfield BIOSCANCTL 0x80field AUTOACKEN 0x40field BIASCANCTL 0x20field BUSFREEREV 0x10field ENDGFORMCHK 0x04field AUTO_MSGOUT_DE 0x02mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE}/** SCSI Status 0*/register SSTAT0 {address 0x04Baccess_mode ROmodes M_DFF0, M_DFF1, M_SCSIfield TARGET 0x80 /* Board acting as target */field SELDO 0x40 /* Selection Done */field SELDI 0x20 /* Board has been selected */field SELINGO 0x10 /* Selection In Progress */field IOERR 0x08 /* LVD Tranceiver mode changed */field OVERRUN 0x04 /* SCSI Offset overrun detected */field SPIORDY 0x02 /* SCSI PIO Ready */field ARBDO 0x01 /* Arbitration Done Out */}/** Clear SCSI Interrupt 0* Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0.*/register CLRSINT0 {address 0x04Baccess_mode WOmodes M_DFF0, M_DFF1, M_SCSIfield CLRSELDO 0x40field CLRSELDI 0x20field CLRSELINGO 0x10field CLRIOERR 0x08field CLROVERRUN 0x04field CLRSPIORDY 0x02field CLRARBDO 0x01}/** SCSI Interrupt Mode 0* Setting any bit will enable the corresponding function* in SIMODE0 to interrupt via the IRQ pin.*/register SIMODE0 {address 0x04Baccess_mode RWmodes M_CFGfield ENSELDO 0x40field ENSELDI 0x20field ENSELINGO 0x10field ENIOERR 0x08field ENOVERRUN 0x04field ENSPIORDY 0x02field ENARBDO 0x01}/** SCSI Status 1*/register SSTAT1 {address 0x04Caccess_mode ROmodes M_DFF0, M_DFF1, M_SCSIfield SELTO 0x80field ATNTARG 0x40field SCSIRSTI 0x20field PHASEMIS 0x10field BUSFREE 0x08field SCSIPERR 0x04field STRB2FAST 0x02field REQINIT 0x01}/** Clear SCSI Interrupt 1* Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1.*/register CLRSINT1 {address 0x04Caccess_mode WOmodes M_DFF0, M_DFF1, M_SCSIfield CLRSELTIMEO 0x80field CLRATNO 0x40field CLRSCSIRSTI 0x20field CLRBUSFREE 0x08field CLRSCSIPERR 0x04field CLRSTRB2FAST 0x02field CLRREQINIT 0x01}/** SCSI Status 2*/register SSTAT2 {address 0x04daccess_mode ROmodes M_DFF0, M_DFF1, M_SCSIfield BUSFREETIME 0xc0 {BUSFREE_LQO 0x40,BUSFREE_DFF0 0x80,BUSFREE_DFF1 0xC0}field NONPACKREQ 0x20field EXP_ACTIVE 0x10 /* SCSI Expander Active */field BSYX 0x08 /* Busy Expander */field WIDE_RES 0x04 /* Modes 0 and 1 only */field SDONE 0x02 /* Modes 0 and 1 only */field DMADONE 0x01 /* Modes 0 and 1 only */}/** Clear SCSI Interrupt 2*/register CLRSINT2 {address 0x04Daccess_mode WOmodes M_DFF0, M_DFF1, M_SCSIfield CLRNONPACKREQ 0x20field CLRWIDE_RES 0x04 /* Modes 0 and 1 only */field CLRSDONE 0x02 /* Modes 0 and 1 only */field CLRDMADONE 0x01 /* Modes 0 and 1 only */}/** SCSI Interrupt Mode 2*/register SIMODE2 {address 0x04Daccess_mode RWmodes M_CFGfield ENWIDE_RES 0x04field ENSDONE 0x02field ENDMADONE 0x01}/** Physical Error Diagnosis*/register PERRDIAG {address 0x04Eaccess_mode ROmodes M_DFF0, M_DFF1, M_SCSIfield HIZERO 0x80field HIPERR 0x40field PREVPHASE 0x20field PARITYERR 0x10field AIPERR 0x08field CRCERR 0x04field DGFORMERR 0x02field DTERR 0x01}/** LQI Manager Current State*/register LQISTATE {address 0x04Eaccess_mode ROmodes M_CFG}/** SCSI Offset Count*/register SOFFCNT {address 0x04Faccess_mode ROmodes M_DFF0, M_DFF1, M_SCSI}/** LQO Manager Current State*/register LQOSTATE {address 0x04Faccess_mode ROmodes M_CFG}/** LQI Manager Status*/register LQISTAT0 {address 0x050access_mode ROmodes M_DFF0, M_DFF1, M_SCSIfield LQIATNQAS 0x20field LQICRCT1 0x10field LQICRCT2 0x08field LQIBADLQT 0x04field LQIATNLQ 0x02field LQIATNCMD 0x01}/** Clear LQI Interrupts 0*/register CLRLQIINT0 {address 0x050access_mode WOmodes M_DFF0, M_DFF1, M_SCSIfield CLRLQIATNQAS 0x20field CLRLQICRCT1 0x10field CLRLQICRCT2 0x08field CLRLQIBADLQT 0x04field CLRLQIATNLQ 0x02field CLRLQIATNCMD 0x01}/** LQI Manager Interrupt Mode 0*/register LQIMODE0 {address 0x050access_mode RWmodes M_CFGfield ENLQIATNQASK 0x20field ENLQICRCT1 0x10field ENLQICRCT2 0x08field ENLQIBADLQT 0x04field ENLQIATNLQ 0x02field ENLQIATNCMD 0x01}/** LQI Manager Status 1*/register LQISTAT1 {address 0x051access_mode ROmodes M_DFF0, M_DFF1, M_SCSIfield LQIPHASE_LQ 0x80field LQIPHASE_NLQ 0x40field LQIABORT 0x20field LQICRCI_LQ 0x10field LQICRCI_NLQ 0x08field LQIBADLQI 0x04field LQIOVERI_LQ 0x02field LQIOVERI_NLQ 0x01}/** Clear LQI Manager Interrupts1*/register CLRLQIINT1 {address 0x051access_mode WOmodes M_DFF0, M_DFF1, M_SCSIfield CLRLQIPHASE_LQ 0x80field CLRLQIPHASE_NLQ 0x40field CLRLIQABORT 0x20field CLRLQICRCI_LQ 0x10field CLRLQICRCI_NLQ 0x08field CLRLQIBADLQI 0x04field CLRLQIOVERI_LQ 0x02field CLRLQIOVERI_NLQ 0x01}/** LQI Manager Interrupt Mode 1*/register LQIMODE1 {address 0x051access_mode RWmodes M_CFGfield ENLQIPHASE_LQ 0x80 /* LQIPHASE1 */field ENLQIPHASE_NLQ 0x40 /* LQIPHASE2 */field ENLIQABORT 0x20field ENLQICRCI_LQ 0x10 /* LQICRCI1 */field ENLQICRCI_NLQ 0x08 /* LQICRCI2 */field ENLQIBADLQI 0x04field ENLQIOVERI_LQ 0x02 /* LQIOVERI1 */field ENLQIOVERI_NLQ 0x01 /* LQIOVERI2 */}/** LQI Manager Status 2*/register LQISTAT2 {address 0x052access_mode ROmodes M_DFF0, M_DFF1, M_SCSIfield PACKETIZED 0x80field LQIPHASE_OUTPKT 0x40field LQIWORKONLQ 0x20field LQIWAITFIFO 0x10field LQISTOPPKT 0x08field LQISTOPLQ 0x04field LQISTOPCMD 0x02field LQIGSAVAIL 0x01}/** SCSI Status 3*/register SSTAT3 {address 0x053access_mode ROmodes M_DFF0, M_DFF1, M_SCSIfield NTRAMPERR 0x02field OSRAMPERR 0x01}/** Clear SCSI Status 3*/register CLRSINT3 {address 0x053access_mode WOmodes M_DFF0, M_DFF1, M_SCSIfield CLRNTRAMPERR 0x02field CLROSRAMPERR 0x01}/** SCSI Interrupt Mode 3*/register SIMODE3 {address 0x053access_mode RWmodes M_CFGfield ENNTRAMPERR 0x02field ENOSRAMPERR 0x01}/** LQO Manager Status 0*/register LQOSTAT0 {address 0x054access_mode ROmodes M_DFF0, M_DFF1, M_SCSIfield LQOTARGSCBPERR 0x10field LQOSTOPT2 0x08field LQOATNLQ 0x04field LQOATNPKT 0x02field LQOTCRC 0x01}/** Clear LQO Manager interrupt 0*/register CLRLQOINT0 {address 0x054access_mode WOmodes M_DFF0, M_DFF1, M_SCSIfield CLRLQOTARGSCBPERR 0x10field CLRLQOSTOPT2 0x08field CLRLQOATNLQ 0x04field CLRLQOATNPKT 0x02field CLRLQOTCRC 0x01}/** LQO Manager Interrupt Mode 0*/register LQOMODE0 {address 0x054access_mode RWmodes M_CFGfield ENLQOTARGSCBPERR 0x10field ENLQOSTOPT2 0x08field ENLQOATNLQ 0x04field ENLQOATNPKT 0x02field ENLQOTCRC 0x01}/** LQO Manager Status 1*/register LQOSTAT1 {address 0x055access_mode ROmodes M_DFF0, M_DFF1, M_SCSIfield LQOINITSCBPERR 0x10field LQOSTOPI2 0x08field LQOBADQAS 0x04field LQOBUSFREE 0x02field LQOPHACHGINPKT 0x01}/** Clear LOQ Interrupt 1*/register CLRLQOINT1 {address 0x055access_mode WOmodes M_DFF0, M_DFF1, M_SCSIfield CLRLQOINITSCBPERR 0x10field CLRLQOSTOPI2 0x08field CLRLQOBADQAS 0x04field CLRLQOBUSFREE 0x02field CLRLQOPHACHGINPKT 0x01}/** LQO Manager Interrupt Mode 1*/register LQOMODE1 {address 0x055access_mode RWmodes M_CFGfield ENLQOINITSCBPERR 0x10field ENLQOSTOPI2 0x08field ENLQOBADQAS 0x04field ENLQOBUSFREE 0x02field ENLQOPHACHGINPKT 0x01}/** LQO Manager Status 2*/register LQOSTAT2 {address 0x056access_mode ROmodes M_DFF0, M_DFF1, M_SCSIfield LQOPKT 0xE0field LQOWAITFIFO 0x10field LQOPHACHGOUTPKT 0x02 /* outside of packet boundaries. */field LQOSTOP0 0x01 /* Stopped after sending all packets */}/** Output Synchronizer Space Count*/register OS_SPACE_CNT {address 0x056access_mode ROmodes M_CFG}/** SCSI Interrupt Mode 1* Setting any bit will enable the corresponding function* in SIMODE1 to interrupt via the IRQ pin.*/register SIMODE1 {address 0x057access_mode RWmodes M_DFF0, M_DFF1, M_SCSIfield ENSELTIMO 0x80field ENATNTARG 0x40field ENSCSIRST 0x20field ENPHASEMIS 0x10field ENBUSFREE 0x08field ENSCSIPERR 0x04field ENSTRB2FAST 0x02field ENREQINIT 0x01}/** Good Status FIFO*/register GSFIFO {address 0x058access_mode ROsize 2modes M_DFF0, M_DFF1, M_SCSI}/** Data FIFO SCSI Transfer Control*/register DFFSXFRCTL {address 0x05Aaccess_mode RWmodes M_DFF0, M_DFF1field DFFBITBUCKET 0x08field CLRSHCNT 0x04field CLRCHN 0x02field RSTCHN 0x01}/** Next SCSI Control Block*/register NEXTSCB {address 0x05Aaccess_mode RWsize 2modes M_SCSI}/* Rev B only. */register LQOSCSCTL {address 0x05Aaccess_mode RWsize 1modes M_CFGfield LQOH2A_VERSION 0x80field LQONOCHKOVER 0x01}/** SEQ Interrupts*/register SEQINTSRC {address 0x05Baccess_mode ROmodes M_DFF0, M_DFF1field CTXTDONE 0x40field SAVEPTRS 0x20field CFG4DATA 0x10field CFG4ISTAT 0x08field CFG4TSTAT 0x04field CFG4ICMD 0x02field CFG4TCMD 0x01}/** Clear Arp Interrupts*/register CLRSEQINTSRC {address 0x05Baccess_mode WOmodes M_DFF0, M_DFF1field CLRCTXTDONE 0x40field CLRSAVEPTRS 0x20field CLRCFG4DATA 0x10field CLRCFG4ISTAT 0x08field CLRCFG4TSTAT 0x04field CLRCFG4ICMD 0x02field CLRCFG4TCMD 0x01}/** SEQ Interrupt Enabled (Shared)*/register SEQIMODE {address 0x05Caccess_mode RWmodes M_DFF0, M_DFF1field ENCTXTDONE 0x40field ENSAVEPTRS 0x20field ENCFG4DATA 0x10field ENCFG4ISTAT 0x08field ENCFG4TSTAT 0x04field ENCFG4ICMD 0x02field ENCFG4TCMD 0x01}/** Current SCSI Control Block*/register CURRSCB {address 0x05Caccess_mode RWsize 2modes M_SCSI}/** Data FIFO Status*/register MDFFSTAT {address 0x05Daccess_mode ROmodes M_DFF0, M_DFF1field SHCNTNEGATIVE 0x40 /* Rev B or higher */field SHCNTMINUS1 0x20 /* Rev B or higher */field LASTSDONE 0x10field SHVALID 0x08field DLZERO 0x04 /* FIFO data ends on packet boundary. */field DATAINFIFO 0x02field FIFOFREE 0x01}/** CRC Control*/register CRCCONTROL {address 0x05daccess_mode RWmodes M_CFGfield CRCVALCHKEN 0x40}/** SCSI Test Control*/register SCSITEST {address 0x05Eaccess_mode RWmodes M_CFGfield CNTRTEST 0x08field SEL_TXPLL_DEBUG 0x04}/** Data FIFO Queue Tag*/register DFFTAG {address 0x05Eaccess_mode RWsize 2modes M_DFF0, M_DFF1}/** Last SCSI Control Block*/register LASTSCB {address 0x05Eaccess_mode RWsize 2modes M_SCSI}/** SCSI I/O Cell Power-down Control*/register IOPDNCTL {address 0x05Faccess_mode RWmodes M_CFGfield DISABLE_OE 0x80field PDN_IDIST 0x04field PDN_DIFFSENSE 0x01}/** Shaddow Host Address.*/register SHADDR {address 0x060access_mode ROsize 8modes M_DFF0, M_DFF1}/** Data Group CRC Interval.*/register DGRPCRCI {address 0x060access_mode RWsize 2modes M_CFG}/** Data Transfer Negotiation Address*/register NEGOADDR {address 0x060access_mode RWmodes M_SCSI}/** Data Transfer Negotiation Data - Period Byte*/register NEGPERIOD {address 0x061access_mode RWmodes M_SCSI}/** Packetized CRC Interval*/register PACKCRCI {address 0x062access_mode RWsize 2modes M_CFG}/** Data Transfer Negotiation Data - Offset Byte*/register NEGOFFSET {address 0x062access_mode RWmodes M_SCSI}/** Data Transfer Negotiation Data - PPR Options*/register NEGPPROPTS {address 0x063access_mode RWmodes M_SCSIfield PPROPT_PACE 0x08field PPROPT_QAS 0x04field PPROPT_DT 0x02field PPROPT_IUT 0x01}/** Data Transfer Negotiation Data - Connection Options*/register NEGCONOPTS {address 0x064access_mode RWmodes M_SCSIfield ENSNAPSHOT 0x40field RTI_WRTDIS 0x20field RTI_OVRDTRN 0x10field ENSLOWCRC 0x08field ENAUTOATNI 0x04field ENAUTOATNO 0x02field WIDEXFER 0x01}/** Negotiation Table Annex Column Index.*/register ANNEXCOL {address 0x065access_mode RWmodes M_SCSI}register SCSCHKN {address 0x066access_mode RWmodes M_CFGfield STSELSKIDDIS 0x40field CURRFIFODEF 0x20field WIDERESEN 0x10field SDONEMSKDIS 0x08field DFFACTCLR 0x04field SHVALIDSTDIS 0x02field LSTSGCLRDIS 0x01}const AHD_ANNEXCOL_PER_DEV0 4const AHD_NUM_PER_DEV_ANNEXCOLS 4const AHD_ANNEXCOL_PRECOMP_SLEW 4const AHD_PRECOMP_MASK 0x07const AHD_PRECOMP_SHIFT 0const AHD_PRECOMP_CUTBACK_17 0x04const AHD_PRECOMP_CUTBACK_29 0x06const AHD_PRECOMP_CUTBACK_37 0x07const AHD_SLEWRATE_MASK 0x78const AHD_SLEWRATE_SHIFT 3/** Rev A has only a single bit (high bit of field) of slew adjustment.* Rev B has 4 bits. The current default happens to be the same for both.*/const AHD_SLEWRATE_DEF_REVA 0x08const AHD_SLEWRATE_DEF_REVB 0x08/* Rev A does not have any amplitude setting. */const AHD_ANNEXCOL_AMPLITUDE 6const AHD_AMPLITUDE_MASK 0x7const AHD_AMPLITUDE_SHIFT 0const AHD_AMPLITUDE_DEF 0x7/** Negotiation Table Annex Data Port.*/register ANNEXDAT {address 0x066access_mode RWmodes M_SCSI}/** Initiator's Own Id.* The SCSI ID to use for Selection Out and seen during a reselection..*/register IOWNID {address 0x067access_mode RWmodes M_SCSI}/** 960MHz Phase-Locked Loop Control 0*/register PLL960CTL0 {address 0x068access_mode RWmodes M_CFGfield PLL_VCOSEL 0x80field PLL_PWDN 0x40field PLL_NS 0x30field PLL_ENLUD 0x08field PLL_ENLPF 0x04field PLL_DLPF 0x02field PLL_ENFBM 0x01}/** Target Own Id*/register TOWNID {address 0x069access_mode RWmodes M_SCSI}/** 960MHz Phase-Locked Loop Control 1*/register PLL960CTL1 {address 0x069access_mode RWmodes M_CFGfield PLL_CNTEN 0x80field PLL_CNTCLR 0x40field PLL_RST 0x01}/** Expander Signature*/register XSIG {address 0x06Aaccess_mode RWmodes M_SCSI}/** Shadow Byte Count*/register SHCNT {address 0x068access_mode RWsize 3modes M_DFF0, M_DFF1}/** Selection Out ID*/register SELOID {address 0x06Baccess_mode RWmodes M_SCSI}/** 960-MHz Phase-Locked Loop Test Count*/register PLL960CNT0 {address 0x06Aaccess_mode ROsize 2modes M_CFG}/** 400-MHz Phase-Locked Loop Control 0*/register PLL400CTL0 {address 0x06Caccess_mode RWmodes M_CFGfield PLL_VCOSEL 0x80field PLL_PWDN 0x40field PLL_NS 0x30field PLL_ENLUD 0x08field PLL_ENLPF 0x04field PLL_DLPF 0x02field PLL_ENFBM 0x01}/** Arbitration Fairness*/register FAIRNESS {address 0x06Caccess_mode RWsize 2modes M_SCSI}/** 400-MHz Phase-Locked Loop Control 1*/register PLL400CTL1 {address 0x06Daccess_mode RWmodes M_CFGfield PLL_CNTEN 0x80field PLL_CNTCLR 0x40field PLL_RST 0x01}/** Arbitration Unfairness*/register UNFAIRNESS {address 0x06Eaccess_mode RWsize 2modes M_SCSI}/** 400-MHz Phase-Locked Loop Test Count*/register PLL400CNT0 {address 0x06Eaccess_mode ROsize 2modes M_CFG}/** SCB Page Pointer*/register SCBPTR {address 0x0A8access_mode RWsize 2modes M_DFF0, M_DFF1, M_CCHAN, M_SCSI}/** CMC SCB Array Count* Number of bytes to transfer between CMC SCB memory and SCBRAM.* Transfers must be 8byte aligned and sized.*/register CCSCBACNT {address 0x0ABaccess_mode RWmodes M_CCHAN}/** SCB Autopointer* SCB-Next Address Snooping logic. When an SCB is transferred to* the card, the next SCB address to be used by the CMC array can* be autoloaded from that transfer.*/register SCBAUTOPTR {address 0x0ABaccess_mode RWmodes M_CFGfield AUSCBPTR_EN 0x80field SCBPTR_ADDR 0x38field SCBPTR_OFF 0x07}/** CMC SG Ram Address Pointer*/register CCSGADDR {address 0x0ACaccess_mode RWmodes M_DFF0, M_DFF1}/** CMC SCB RAM Address Pointer*/register CCSCBADDR {address 0x0ACaccess_mode RWmodes M_CCHAN}/** CMC SCB Ram Back-up Address Pointer* Indicates the true stop location of transfers halted prior* to SCBHCNT going to 0.*/register CCSCBADR_BK {address 0x0ACaccess_mode ROmodes M_CFG}/** CMC SG Control*/register CCSGCTL {address 0x0ADaccess_mode RWmodes M_DFF0, M_DFF1field CCSGDONE 0x80field SG_CACHE_AVAIL 0x10field CCSGENACK 0x08mask CCSGEN 0x0Cfield SG_FETCH_REQ 0x02field CCSGRESET 0x01}/** CMD SCB Control*/register CCSCBCTL {address 0x0ADaccess_mode RWmodes M_CCHANfield CCSCBDONE 0x80field ARRDONE 0x40field CCARREN 0x10field CCSCBEN 0x08field CCSCBDIR 0x04field CCSCBRESET 0x01}/** CMC Ram BIST*/register CMC_RAMBIST {address 0x0ADaccess_mode RWmodes M_CFGfield SG_ELEMENT_SIZE 0x80field SCBRAMBIST_FAIL 0x40field SG_BIST_FAIL 0x20field SG_BIST_EN 0x10field CMC_BUFFER_BIST_FAIL 0x02field CMC_BUFFER_BIST_EN 0x01}/** CMC SG RAM Data Port*/register CCSGRAM {address 0x0B0access_mode RWmodes M_DFF0, M_DFF1}/** CMC SCB RAM Data Port*/register CCSCBRAM {address 0x0B0access_mode RWmodes M_CCHAN}/** Flex DMA Address.*/register FLEXADR {address 0x0B0access_mode RWsize 3modes M_SCSI}/** Flex DMA Byte Count*/register FLEXCNT {address 0x0B3access_mode RWsize 2modes M_SCSI}/** Flex DMA Status*/register FLEXDMASTAT {address 0x0B5access_mode RWmodes M_SCSIfield FLEXDMAERR 0x02field FLEXDMADONE 0x01}/** Flex DMA Data Port*/register FLEXDATA {address 0x0B6access_mode RWmodes M_SCSI}/** Board Data*/register BRDDAT {address 0x0B8access_mode RWmodes M_SCSI}/** Board Control*/register BRDCTL {address 0x0B9access_mode RWmodes M_SCSIfield FLXARBACK 0x80field FLXARBREQ 0x40field BRDADDR 0x38field BRDEN 0x04field BRDRW 0x02field BRDSTB 0x01}/** Serial EEPROM Address*/register SEEADR {address 0x0BAaccess_mode RWmodes M_SCSI}/** Serial EEPROM Data*/register SEEDAT {address 0x0BCaccess_mode RWsize 2modes M_SCSI}/** Serial EEPROM Status*/register SEESTAT {address 0x0BEaccess_mode ROmodes M_SCSIfield INIT_DONE 0x80field SEEOPCODE 0x70field LDALTID_L 0x08field SEEARBACK 0x04field SEEBUSY 0x02field SEESTART 0x01}/** Serial EEPROM Control*/register SEECTL {address 0x0BEaccess_mode RWmodes M_SCSIfield SEEOPCODE 0x70 {SEEOP_ERASE 0x70,SEEOP_READ 0x60,SEEOP_WRITE 0x50,/** The following four commands use special* addresses for differentiation.*/SEEOP_ERAL 0x40}mask SEEOP_EWEN 0x40mask SEEOP_WALL 0x40mask SEEOP_EWDS 0x40field SEERST 0x02field SEESTART 0x01}const SEEOP_ERAL_ADDR 0x80const SEEOP_EWEN_ADDR 0xC0const SEEOP_WRAL_ADDR 0x40const SEEOP_EWDS_ADDR 0x00/** SCB Counter*/register SCBCNT {address 0x0BFaccess_mode RWmodes M_SCSI}/** Data FIFO Write Address* Pointer to the next QWD location to be written to the data FIFO.*/register DFWADDR {address 0x0C0access_mode RWsize 2modes M_DFF0, M_DFF1}/** DSP Filter Control*/register DSPFLTRCTL {address 0x0C0access_mode RWmodes M_CFGfield FLTRDISABLE 0x20field EDGESENSE 0x10field DSPFCNTSEL 0x0F}/** DSP Data Channel Control*/register DSPDATACTL {address 0x0C1access_mode RWmodes M_CFGfield BYPASSENAB 0x80field DESQDIS 0x10field RCVROFFSTDIS 0x04field XMITOFFSTDIS 0x02}/** Data FIFO Read Address* Pointer to the next QWD location to be read from the data FIFO.*/register DFRADDR {address 0x0C2access_mode RWsize 2modes M_DFF0, M_DFF1}/** DSP REQ Control*/register DSPREQCTL {address 0x0C2access_mode RWmodes M_CFGfield MANREQCTL 0xC0field MANREQDLY 0x3F}/** DSP ACK Control*/register DSPACKCTL {address 0x0C3access_mode RWmodes M_CFGfield MANACKCTL 0xC0field MANACKDLY 0x3F}/** Data FIFO Data* Read/Write byte port into the data FIFO. The read and write* FIFO pointers increment with each read and write respectively* to this port.*/register DFDAT {address 0x0C4access_mode RWmodes M_DFF0, M_DFF1}/** DSP Channel Select*/register DSPSELECT {address 0x0C4access_mode RWmodes M_CFGfield AUTOINCEN 0x80field DSPSEL 0x1F}const NUMDSPS 0x14/** Write Bias Control*/register WRTBIASCTL {address 0x0C5access_mode WOmodes M_CFGfield AUTOXBCDIS 0x80field XMITMANVAL 0x3F}/** Currently the WRTBIASCTL is the same as the default.*/const WRTBIASCTL_HP_DEFAULT 0x0/** Receiver Bias Control*/register RCVRBIOSCTL {address 0x0C6access_mode WOmodes M_CFGfield AUTORBCDIS 0x80field RCVRMANVAL 0x3F}/** Write Bias Calculator*/register WRTBIASCALC {address 0x0C7access_mode ROmodes M_CFG}/** Data FIFO Pointers* Contains the byte offset from DFWADDR and DWRADDR to the current* FIFO write/read locations.*/register DFPTRS {address 0x0C8access_mode RWmodes M_DFF0, M_DFF1}/** Receiver Bias Calculator*/register RCVRBIASCALC {address 0x0C8access_mode ROmodes M_CFG}/** Data FIFO Backup Read Pointer* Contains the data FIFO address to be restored if the last* data accessed from the data FIFO was not transferred successfully.*/register DFBKPTR {address 0x0C9access_mode RWsize 2modes M_DFF0, M_DFF1}/** Skew Calculator*/register SKEWCALC {address 0x0C9access_mode ROmodes M_CFG}/** Data FIFO Debug Control*/register DFDBCTL {address 0x0CBaccess_mode RWmodes M_DFF0, M_DFF1field DFF_CIO_WR_RDY 0x20field DFF_CIO_RD_RDY 0x10field DFF_DIR_ERR 0x08field DFF_RAMBIST_FAIL 0x04field DFF_RAMBIST_DONE 0x02field DFF_RAMBIST_EN 0x01}/** Data FIFO Space Count* Number of FIFO locations that are free.*/register DFSCNT {address 0x0CCaccess_mode ROsize 2modes M_DFF0, M_DFF1}/** Data FIFO Byte Count* Number of filled FIFO locations.*/register DFBCNT {address 0x0CEaccess_mode ROsize 2modes M_DFF0, M_DFF1}/** Sequencer Program Overlay Address.* Low address must be written prior to high address.*/register OVLYADDR {address 0x0D4modes M_SCSIsize 2access_mode RW}/** Sequencer Control 0* Error detection mode, speed configuration,* single step, breakpoints and program load.*/register SEQCTL0 {address 0x0D6access_mode RWfield PERRORDIS 0x80field PAUSEDIS 0x40field FAILDIS 0x20field FASTMODE 0x10field BRKADRINTEN 0x08field STEP 0x04field SEQRESET 0x02field LOADRAM 0x01}/** Sequencer Control 1* Instruction RAM Diagnostics*/register SEQCTL1 {address 0x0D7access_mode RWfield OVRLAY_DATA_CHK 0x08field RAMBIST_DONE 0x04field RAMBIST_FAIL 0x02field RAMBIST_EN 0x01}/** Sequencer Flags* Zero and Carry state of the ALU.*/register FLAGS {address 0x0D8access_mode ROfield ZERO 0x02field CARRY 0x01}/** Sequencer Interrupt Control*/register SEQINTCTL {address 0x0D9access_mode RWfield INTVEC1DSL 0x80field INT1_CONTEXT 0x20field SCS_SEQ_INT1M1 0x10field SCS_SEQ_INT1M0 0x08field INTMASK2 0x04field INTMASK1 0x02field IRET 0x01}/** Sequencer RAM Data Port* Single byte window into the Sequencer Instruction Ram area starting* at the address specified by OVLYADDR. To write a full instruction word,* simply write four bytes in succession. OVLYADDR will increment after the* most significant instrution byte (the byte with the parity bit) is written.*/register SEQRAM {address 0x0DAaccess_mode RW}/** Sequencer Program Counter* Low byte must be written prior to high byte.*/register PRGMCNT {address 0x0DEaccess_mode RWsize 2}/** Accumulator*/register ACCUM {address 0x0E0access_mode RWaccumulator}/** Source Index Register* Incrementing index for reads of SINDIR and the destination (low byte only)* for any immediate operands passed in jmp, jc, jnc, call instructions.* Example:* mvi 0xFF call some_routine;** Will set SINDEX[0] to 0xFF and call the routine "some_routine.*/register SINDEX {address 0x0E2access_mode RWsize 2sindex}/** Destination Index Register* Incrementing index for writes to DINDIR. Can be used as a scratch register.*/register DINDEX {address 0x0E4access_mode RWsize 2}/** Break Address* Sequencer instruction breakpoint address address.*/register BRKADDR0 {address 0x0E6access_mode RW}register BRKADDR1 {address 0x0E6access_mode RWfield BRKDIS 0x80 /* Disable Breakpoint */}/** All Ones* All reads to this register return the value 0xFF.*/register ALLONES {address 0x0E8access_mode ROallones}/** All Zeros* All reads to this register return the value 0.*/register ALLZEROS {address 0x0EAaccess_mode ROallzeros}/** No Destination* Writes to this register have no effect.*/register NONE {address 0x0EAaccess_mode WOnone}/** Source Index Indirect* Reading this register is equivalent to reading (register_base + SINDEX) and* incrementing SINDEX by 1.*/register SINDIR {address 0x0ECaccess_mode RO}/** Destination Index Indirect* Writing this register is equivalent to writing to (register_base + DINDEX)* and incrementing DINDEX by 1.*/register DINDIR {address 0x0EDaccess_mode WO}/** Function One* 2's complement to bit value conversion. Write the 2's complement value* (0-7 only) to the top nibble and retrieve the bit indexed by that value* on the next read of this register.* Example:* Write 0x60* Read 0x40*/register FUNCTION1 {address 0x0F0access_mode RW}/** Stack* Window into the stack. Each stack location is 10 bits wide reported* low byte followed by high byte. There are 8 stack locations.*/register STACK {address 0x0F2access_mode RW}/** Interrupt Vector 1 Address* Interrupt branch address for SCS SEQ_INT1 mode 0 and 1 interrupts.*/register INTVEC1_ADDR {address 0x0F4access_mode RWsize 2modes M_CFG}/** Current Address* Address of the SEQRAM instruction currently executing instruction.*/register CURADDR {address 0x0F4access_mode RWsize 2modes M_SCSI}/** Interrupt Vector 2 Address* Interrupt branch address for HST_SEQ_INT2 interrupts.*/register INTVEC2_ADDR {address 0x0F6access_mode RWsize 2modes M_CFG}/** Last Address* Address of the SEQRAM instruction executed prior to the current instruction.*/register LASTADDR {address 0x0F6access_mode RWsize 2modes M_SCSI}register AHD_PCI_CONFIG_BASE {address 0x100access_mode RWsize 256modes M_CFG}/* ---------------------- Scratch RAM Offsets ------------------------- */scratch_ram {/* Mode Specific */address 0x0A0size 8modes 0, 1, 2, 3REG0 {size 2}REG1 {size 2}REG_ISR {size 2}SG_STATE {size 1field SEGS_AVAIL 0x01field LOADING_NEEDED 0x02field FETCH_INPROG 0x04}/** Track whether the transfer byte count for* the current data phase is odd.*/DATA_COUNT_ODD {size 1}}scratch_ram {/* Mode Specific */address 0x0F8size 8modes 0, 1, 2, 3LONGJMP_ADDR {size 2}ACCUM_SAVE {size 1}}scratch_ram {address 0x100size 128modes 0, 1, 2, 3/** Per "other-id" execution queues. We use an array of* tail pointers into lists of SCBs sorted by "other-id".* The execution head pointer threads the head SCBs for* each list.*/WAITING_SCB_TAILS {size 32}WAITING_TID_HEAD {size 2}WAITING_TID_TAIL {size 2}/** SCBID of the next SCB in the new SCB queue.*/NEXT_QUEUED_SCB_ADDR {size 4}/** head of list of SCBs that have* completed but have not been* put into the qoutfifo.*/COMPLETE_SCB_HEAD {size 2}/** The list of completed SCBs in* the active DMA.*/COMPLETE_SCB_DMAINPROG_HEAD {size 2}/** head of list of SCBs that have* completed but need to be uploaded* to the host prior to being completed.*/COMPLETE_DMA_SCB_HEAD {size 2}/* Counting semaphore to prevent new select-outs */QFREEZE_COUNT {size 2}/** Mode to restore on legacy idle loop exit.*/SAVED_MODE {size 1}/** Single byte buffer used to designate the type or message* to send to a target.*/MSG_OUT {size 1}/* Parameters for DMA Logic */DMAPARAMS {size 1field PRELOADEN 0x80field WIDEODD 0x40field SCSIEN 0x20field SDMAEN 0x10field SDMAENACK 0x10field HDMAEN 0x08field HDMAENACK 0x08field DIRECTION 0x04 /* Set indicates PCI->SCSI */field FIFOFLUSH 0x02field FIFORESET 0x01}SEQ_FLAGS {size 1field NOT_IDENTIFIED 0x80field NO_CDB_SENT 0x40field TARGET_CMD_IS_TAGGED 0x40field DPHASE 0x20/* Target flags */field TARG_CMD_PENDING 0x10field CMDPHASE_PENDING 0x08field DPHASE_PENDING 0x04field SPHASE_PENDING 0x02field NO_DISCONNECT 0x01}/** Temporary storage for the* target/channel/lun of a* reconnecting target*/SAVED_SCSIID {size 1}SAVED_LUN {size 1}/** The last bus phase as seen by the sequencer.*/LASTPHASE {size 1field CDI 0x80field IOI 0x40field MSGI 0x20field P_BUSFREE 0x01enum PHASE_MASK CDO|IOO|MSGO {P_DATAOUT 0x0,P_DATAIN IOO,P_DATAOUT_DT P_DATAOUT|MSGO,P_DATAIN_DT P_DATAIN|MSGO,P_COMMAND CDO,P_MESGOUT CDO|MSGO,P_STATUS CDO|IOO,P_MESGIN CDO|IOO|MSGO}}/** Value to "or" into the SCBPTR[1] value to* indicate that an entry in the QINFIFO is valid.*/QOUTFIFO_ENTRY_VALID_TAG {size 1}/** Base address of our shared data with the kernel driver in host* memory. This includes the qoutfifo and target mode* incoming command queue.*/SHARED_DATA_ADDR {size 4}/** Pointer to location in host memory for next* position in the qoutfifo.*/QOUTFIFO_NEXT_ADDR {size 4}/** Kernel and sequencer offsets into the queue of* incoming target mode command descriptors. The* queue is full when the KERNEL_TQINPOS == TQINPOS.*/KERNEL_TQINPOS {size 1}TQINPOS {size 1}ARG_1 {size 1mask SEND_MSG 0x80mask SEND_SENSE 0x40mask SEND_REJ 0x20mask MSGOUT_PHASEMIS 0x10mask EXIT_MSG_LOOP 0x08mask CONT_MSG_LOOP_WRITE 0x04mask CONT_MSG_LOOP_READ 0x03mask CONT_MSG_LOOP_TARG 0x02alias RETURN_1}ARG_2 {size 1alias RETURN_2}/** Snapshot of MSG_OUT taken after each message is sent.*/LAST_MSG {size 1}/** Sequences the kernel driver has okayed for us. This allows* the driver to do things like prevent initiator or target* operations.*/SCSISEQ_TEMPLATE {size 1field MANUALCTL 0x40field ENSELI 0x20field ENRSELI 0x10field MANUALP 0x0Cfield ENAUTOATNP 0x02field ALTSTIM 0x01}/** The initiator specified tag for this target mode transaction.*/INITIATOR_TAG {size 1}SEQ_FLAGS2 {size 1field TARGET_MSG_PENDING 0x02field SELECTOUT_QFROZEN 0x04}ALLOCFIFO_SCBPTR {size 2}/** The maximum amount of time to wait, when interrupt coalescing* is enabled, before issueing a CMDCMPLT interrupt for a completed* command.*/INT_COALESCING_TIMER {size 2}/** The maximum number of commands to coalesce into a single interrupt.* Actually the 2's complement of that value to simplify sequencer* code.*/INT_COALESCING_MAXCMDS {size 1}/** The minimum number of commands still outstanding required* to continue coalescing (2's complement of value).*/INT_COALESCING_MINCMDS {size 1}/** Number of commands "in-flight".*/CMDS_PENDING {size 2}/** The count of commands that have been coalesced.*/INT_COALESCING_CMDCOUNT {size 1}/** Since the HS_MAIBOX is self clearing, copy its contents to* this position in scratch ram every time it changes.*/LOCAL_HS_MAILBOX {size 1}/** Target-mode CDB type to CDB length table used* in non-packetized operation.*/CMDSIZE_TABLE {size 8}}/************************* Hardware SCB Definition ****************************/scb {address 0x180size 64modes 0, 1, 2, 3SCB_RESIDUAL_DATACNT {size 4alias SCB_CDB_STOREalias SCB_HOST_CDB_PTR}SCB_RESIDUAL_SGPTR {size 4field SG_ADDR_MASK 0xf8 /* In the last byte */field SG_OVERRUN_RESID 0x02 /* In the first byte */field SG_LIST_NULL 0x01 /* In the first byte */}SCB_SCSI_STATUS {size 1alias SCB_HOST_CDB_LEN}SCB_TARGET_PHASES {size 1}SCB_TARGET_DATA_DIR {size 1}SCB_TARGET_ITAG {size 1}SCB_SENSE_BUSADDR {/** Only valid if CDB length is less than 13 bytes or* we are using a CDB pointer. Otherwise contains* the last 4 bytes of embedded cdb information.*/size 4alias SCB_NEXT_COMPLETE}SCB_TAG {alias SCB_FIFO_USE_COUNTsize 2}SCB_CONTROL {size 1field TARGET_SCB 0x80field DISCENB 0x40field TAG_ENB 0x20field MK_MESSAGE 0x10field STATUS_RCVD 0x08field DISCONNECTED 0x04field SCB_TAG_TYPE 0x03}SCB_SCSIID {size 1field TID 0xF0field OID 0x0F}SCB_LUN {size 1field LID 0xff}SCB_TASK_ATTRIBUTE {size 1/** Overloaded field for non-packetized* ignore wide residue message handling.*/field SCB_XFERLEN_ODD 0x01}SCB_CDB_LEN {size 1field SCB_CDB_LEN_PTR 0x80 /* CDB in host memory */}SCB_TASK_MANAGEMENT {size 1}SCB_DATAPTR {size 8}SCB_DATACNT {/** The last byte is really the high address bits for* the data address.*/size 4field SG_LAST_SEG 0x80 /* In the fourth byte */field SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */}SCB_SGPTR {size 4field SG_STATUS_VALID 0x04 /* In the first byte */field SG_FULL_RESID 0x02 /* In the first byte */field SG_LIST_NULL 0x01 /* In the first byte */}SCB_BUSADDR {size 4}SCB_NEXT {alias SCB_NEXT_SCB_BUSADDRsize 2}SCB_NEXT2 {size 2}SCB_SPARE {size 8alias SCB_PKT_LUN}SCB_DISCONNECTED_LISTS {size 8}}/*********************************** Constants ********************************/const MK_MESSAGE_BIT_OFFSET 4const TID_SHIFT 4const TARGET_CMD_CMPLT 0xfeconst INVALID_ADDR 0x80#define SCB_LIST_NULL 0xff#define QOUTFIFO_ENTRY_VALID_TOGGLE 0x80const CCSGADDR_MAX 0x80const CCSCBADDR_MAX 0x80const CCSGRAM_MAXSEGS 16/* Selection Timeout Timer Constants */const STIMESEL_SHIFT 3const STIMESEL_MIN 0x18const STIMESEL_BUG_ADJ 0x8/* WDTR Message values */const BUS_8_BIT 0x00const BUS_16_BIT 0x01const BUS_32_BIT 0x02/* Offset maximums */const MAX_OFFSET 0xfeconst MAX_OFFSET_PACED 0xfeconst MAX_OFFSET_PACED_BUG 0x7f/** Some 160 devices incorrectly accept 0xfe as a* sync offset, but will overrun this value. Limit* to 0x7f for speed lower than U320 which will* avoid the persistent sync offset overruns.*/const MAX_OFFSET_NON_PACED 0x7fconst HOST_MSG 0xff/** The size of our sense buffers.* Sense buffer mapping can be handled in either of two ways.* The first is to allocate a dmamap for each transaction.* Depending on the architecture, dmamaps can be costly. The* alternative is to statically map the buffers in much the same* way we handle our scatter gather lists. The driver implements* the later.*/const AHD_SENSE_BUFSIZE 256/* Target mode command processing constants */const CMD_GROUP_CODE_SHIFT 0x05const STATUS_BUSY 0x08const STATUS_QUEUE_FULL 0x28const STATUS_PKT_SENSE 0xFFconst TARGET_DATA_IN 1const SCB_TRANSFER_SIZE_FULL_LUN 56const SCB_TRANSFER_SIZE_1BYTE_LUN 48/* PKT_OVERRUN_BUFSIZE must be a multiple of 256 less than 64K */const PKT_OVERRUN_BUFSIZE 512/** Timer parameters.*/const AHD_TIMER_US_PER_TICK 25const AHD_TIMER_MAX_TICKS 0xFFFFconst AHD_TIMER_MAX_US (AHD_TIMER_MAX_TICKS * AHD_TIMER_US_PER_TICK)/** Downloaded (kernel inserted) constants*/const SG_PREFETCH_CNT downloadconst SG_PREFETCH_CNT_LIMIT downloadconst SG_PREFETCH_ALIGN_MASK downloadconst SG_PREFETCH_ADDR_MASK downloadconst SG_SIZEOF downloadconst PKT_OVERRUN_BUFOFFSET downloadconst SCB_TRANSFER_SIZE download/** BIOS SCB offsets*/const NVRAM_SCB_OFFSET 0x2C