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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [drivers/] [scsi/] [aic7xxx/] [aic7xxx.reg] - Rev 1765
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/** Aic7xxx register and scratch ram definitions.** Copyright (c) 1994-2001 Justin T. Gibbs.* Copyright (c) 2000-2001 Adaptec Inc.* All rights reserved.** Redistribution and use in source and binary forms, with or without* modification, are permitted provided that the following conditions* are met:* 1. Redistributions of source code must retain the above copyright* notice, this list of conditions, and the following disclaimer,* without modification.* 2. Redistributions in binary form must reproduce at minimum a disclaimer* substantially similar to the "NO WARRANTY" disclaimer below* ("Disclaimer") and any redistribution must be conditioned upon* including a substantially similar Disclaimer requirement for further* binary redistribution.* 3. Neither the names of the above-listed copyright holders nor the names* of any contributors may be used to endorse or promote products derived* from this software without specific prior written permission.** Alternatively, this software may be distributed under the terms of the* GNU General Public License ("GPL") version 2 as published by the Free* Software Foundation.** NO WARRANTY* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE* POSSIBILITY OF SUCH DAMAGES.** $FreeBSD$*/VERSION = "$Id: aic7xxx.reg,v 1.1.1.1 2004-04-15 02:16:19 phoenix Exp $"/** This file is processed by the aic7xxx_asm utility for use in assembling* firmware for the aic7xxx family of SCSI host adapters as well as to generate* a C header file for use in the kernel portion of the Aic7xxx driver.** All page numbers refer to the Adaptec AIC-7770 Data Book available from* Adaptec's Technical Documents Department 1-800-934-2766*//** SCSI Sequence Control (p. 3-11).* Each bit, when set starts a specific SCSI sequence on the bus*/register SCSISEQ {address 0x000access_mode RWfield TEMODE 0x80field ENSELO 0x40field ENSELI 0x20field ENRSELI 0x10field ENAUTOATNO 0x08field ENAUTOATNI 0x04field ENAUTOATNP 0x02field SCSIRSTO 0x01}/** SCSI Transfer Control 0 Register (pp. 3-13).* Controls the SCSI module data path.*/register SXFRCTL0 {address 0x001access_mode RWfield DFON 0x80field DFPEXP 0x40field FAST20 0x20field CLRSTCNT 0x10field SPIOEN 0x08field SCAMEN 0x04field CLRCHN 0x02}/** SCSI Transfer Control 1 Register (pp. 3-14,15).* Controls the SCSI module data path.*/register SXFRCTL1 {address 0x002access_mode RWfield BITBUCKET 0x80field SWRAPEN 0x40field ENSPCHK 0x20mask STIMESEL 0x18field ENSTIMER 0x04field ACTNEGEN 0x02field STPWEN 0x01 /* Powered Termination */}/** SCSI Control Signal Read Register (p. 3-15).* Reads the actual state of the SCSI bus pins*/register SCSISIGI {address 0x003access_mode ROfield CDI 0x80field IOI 0x40field MSGI 0x20field ATNI 0x10field SELI 0x08field BSYI 0x04field REQI 0x02field ACKI 0x01/** Possible phases in SCSISIGI*/mask PHASE_MASK CDI|IOI|MSGImask P_DATAOUT 0x00mask P_DATAIN IOImask P_DATAOUT_DT P_DATAOUT|MSGImask P_DATAIN_DT P_DATAIN|MSGImask P_COMMAND CDImask P_MESGOUT CDI|MSGImask P_STATUS CDI|IOImask P_MESGIN CDI|IOI|MSGI}/** SCSI Control Signal Write Register (p. 3-16).* Writing to this register modifies the control signals on the bus. Only* those signals that are allowed in the current mode (Initiator/Target) are* asserted.*/register SCSISIGO {address 0x003access_mode WOfield CDO 0x80field IOO 0x40field MSGO 0x20field ATNO 0x10field SELO 0x08field BSYO 0x04field REQO 0x02field ACKO 0x01/** Possible phases to write into SCSISIG0*/mask PHASE_MASK CDI|IOI|MSGImask P_DATAOUT 0x00mask P_DATAIN IOImask P_COMMAND CDImask P_MESGOUT CDI|MSGImask P_STATUS CDI|IOImask P_MESGIN CDI|IOI|MSGI}/** SCSI Rate Control (p. 3-17).* Contents of this register determine the Synchronous SCSI data transfer* rate and the maximum synchronous Req/Ack offset. An offset of 0 in the* SOFS (3:0) bits disables synchronous data transfers. Any offset value* greater than 0 enables synchronous transfers.*/register SCSIRATE {address 0x004access_mode RWfield WIDEXFER 0x80 /* Wide transfer control */field ENABLE_CRC 0x40 /* CRC for D-Phases */field SINGLE_EDGE 0x10 /* Disable DT Transfers */mask SXFR 0x70 /* Sync transfer rate */mask SXFR_ULTRA2 0x0f /* Sync transfer rate */mask SOFS 0x0f /* Sync offset */}/** SCSI ID (p. 3-18).* Contains the ID of the board and the current target on the* selected channel.*/register SCSIID {address 0x005access_mode RWmask TID 0xf0 /* Target ID mask */mask TWIN_TID 0x70field TWIN_CHNLB 0x80mask OID 0x0f /* Our ID mask *//** SCSI Maximum Offset (p. 4-61 aic7890/91 Data Book)* The aic7890/91 allow an offset of up to 127 transfers in both wide* and narrow mode.*/alias SCSIOFFSETmask SOFS_ULTRA2 0x7f /* Sync offset U2 chips */}/** SCSI Latched Data (p. 3-19).* Read/Write latches used to transfer data on the SCSI bus during* Automatic or Manual PIO mode. SCSIDATH can be used for the* upper byte of a 16bit wide asynchronouse data phase transfer.*/register SCSIDATL {address 0x006access_mode RW}register SCSIDATH {address 0x007access_mode RW}/** SCSI Transfer Count (pp. 3-19,20)* These registers count down the number of bytes transferred* across the SCSI bus. The counter is decremented only once* the data has been safely transferred. SDONE in SSTAT0 is* set when STCNT goes to 0*/register STCNT {address 0x008size 3access_mode RW}/* ALT_MODE registers (Ultra2 and Ultra160 chips) */register SXFRCTL2 {address 0x013access_mode RWfield AUTORSTDIS 0x10field CMDDMAEN 0x08mask ASYNC_SETUP 0x07}/* ALT_MODE register on Ultra160 chips */register OPTIONMODE {address 0x008access_mode RWfield AUTORATEEN 0x80field AUTOACKEN 0x40field ATNMGMNTEN 0x20field BUSFREEREV 0x10field EXPPHASEDIS 0x08field SCSIDATL_IMGEN 0x04field AUTO_MSGOUT_DE 0x02field DIS_MSGIN_DUALEDGE 0x01mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE|DIS_MSGIN_DUALEDGE}/* ALT_MODE register on Ultra160 chips */register TARGCRCCNT {address 0x00asize 2access_mode RW}/** Clear SCSI Interrupt 0 (p. 3-20)* Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0.*/register CLRSINT0 {address 0x00baccess_mode WOfield CLRSELDO 0x40field CLRSELDI 0x20field CLRSELINGO 0x10field CLRSWRAP 0x08field CLRIOERR 0x08 /* Ultra2 Only */field CLRSPIORDY 0x02}/** SCSI Status 0 (p. 3-21)* Contains one set of SCSI Interrupt codes* These are most likely of interest to the sequencer*/register SSTAT0 {address 0x00baccess_mode ROfield TARGET 0x80 /* Board acting as target */field SELDO 0x40 /* Selection Done */field SELDI 0x20 /* Board has been selected */field SELINGO 0x10 /* Selection In Progress */field SWRAP 0x08 /* 24bit counter wrap */field IOERR 0x08 /* LVD Tranceiver mode changed */field SDONE 0x04 /* STCNT = 0x000000 */field SPIORDY 0x02 /* SCSI PIO Ready */field DMADONE 0x01 /* DMA transfer completed */}/** Clear SCSI Interrupt 1 (p. 3-23)* Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1.*/register CLRSINT1 {address 0x00caccess_mode WOfield CLRSELTIMEO 0x80field CLRATNO 0x40field CLRSCSIRSTI 0x20field CLRBUSFREE 0x08field CLRSCSIPERR 0x04field CLRPHASECHG 0x02field CLRREQINIT 0x01}/** SCSI Status 1 (p. 3-24)*/register SSTAT1 {address 0x00caccess_mode ROfield SELTO 0x80field ATNTARG 0x40field SCSIRSTI 0x20field PHASEMIS 0x10field BUSFREE 0x08field SCSIPERR 0x04field PHASECHG 0x02field REQINIT 0x01}/** SCSI Status 2 (pp. 3-25,26)*/register SSTAT2 {address 0x00daccess_mode ROfield OVERRUN 0x80field SHVALID 0x40 /* Shaddow Layer non-zero */field EXP_ACTIVE 0x10 /* SCSI Expander Active */field CRCVALERR 0x08 /* CRC doesn't match (U3 only) */field CRCENDERR 0x04 /* No terminal CRC packet (U3 only) */field CRCREQERR 0x02 /* Illegal CRC packet req (U3 only) */field DUAL_EDGE_ERR 0x01 /* Incorrect data phase (U3 only) */mask SFCNT 0x1f}/** SCSI Status 3 (p. 3-26)*/register SSTAT3 {address 0x00eaccess_mode ROmask SCSICNT 0xf0mask OFFCNT 0x0fmask U2OFFCNT 0x7f}/** SCSI ID for the aic7890/91 chips*/register SCSIID_ULTRA2 {address 0x00faccess_mode RWmask TID 0xf0 /* Target ID mask */mask OID 0x0f /* Our ID mask */}/** SCSI Interrupt Mode 1 (p. 3-28)* Setting any bit will enable the corresponding function* in SIMODE0 to interrupt via the IRQ pin.*/register SIMODE0 {address 0x010access_mode RWfield ENSELDO 0x40field ENSELDI 0x20field ENSELINGO 0x10field ENSWRAP 0x08field ENIOERR 0x08 /* LVD Tranceiver mode changes */field ENSDONE 0x04field ENSPIORDY 0x02field ENDMADONE 0x01}/** SCSI Interrupt Mode 1 (pp. 3-28,29)* Setting any bit will enable the corresponding function* in SIMODE1 to interrupt via the IRQ pin.*/register SIMODE1 {address 0x011access_mode RWfield ENSELTIMO 0x80field ENATNTARG 0x40field ENSCSIRST 0x20field ENPHASEMIS 0x10field ENBUSFREE 0x08field ENSCSIPERR 0x04field ENPHASECHG 0x02field ENREQINIT 0x01}/** SCSI Data Bus (High) (p. 3-29)* This register reads data on the SCSI Data bus directly.*/register SCSIBUSL {address 0x012access_mode RW}register SCSIBUSH {address 0x013access_mode RW}/** SCSI/Host Address (p. 3-30)* These registers hold the host address for the byte about to be* transferred on the SCSI bus. They are counted up in the same* manner as STCNT is counted down. SHADDR should always be used* to determine the address of the last byte transferred since HADDR* can be skewed by write ahead.*/register SHADDR {address 0x014size 4access_mode RO}/** Selection Timeout Timer (p. 3-30)*/register SELTIMER {address 0x018access_mode RWfield STAGE6 0x20field STAGE5 0x10field STAGE4 0x08field STAGE3 0x04field STAGE2 0x02field STAGE1 0x01alias TARGIDIN}/** Selection/Reselection ID (p. 3-31)* Upper four bits are the device id. The ONEBIT is set when the re/selecting* device did not set its own ID.*/register SELID {address 0x019access_mode RWmask SELID_MASK 0xf0field ONEBIT 0x08}register SCAMCTL {address 0x01aaccess_mode RWfield ENSCAMSELO 0x80field CLRSCAMSELID 0x40field ALTSTIM 0x20field DFLTTID 0x10mask SCAMLVL 0x03}/** Target Mode Selecting in ID bitmask (aic7890/91/96/97)*/register TARGID {address 0x01bsize 2access_mode RW}/** Serial Port I/O Cabability register (p. 4-95 aic7860 Data Book)* Indicates if external logic has been attached to the chip to* perform the tasks of accessing a serial eeprom, testing termination* strength, and performing cable detection. On the aic7860, most of* these features are handled on chip, but on the aic7855 an attached* aic3800 does the grunt work.*/register SPIOCAP {address 0x01baccess_mode RWfield SOFT1 0x80field SOFT0 0x40field SOFTCMDEN 0x20field EXT_BRDCTL 0x10 /* External Board control */field SEEPROM 0x08 /* External serial eeprom logic */field EEPROM 0x04 /* Writable external BIOS ROM */field ROM 0x02 /* Logic for accessing external ROM */field SSPIOCPS 0x01 /* Termination and cable detection */}register BRDCTL {address 0x01dfield BRDDAT7 0x80field BRDDAT6 0x40field BRDDAT5 0x20field BRDSTB 0x10field BRDCS 0x08field BRDRW 0x04field BRDCTL1 0x02field BRDCTL0 0x01/* 7890 Definitions */field BRDDAT4 0x10field BRDDAT3 0x08field BRDDAT2 0x04field BRDRW_ULTRA2 0x02field BRDSTB_ULTRA2 0x01}/** Serial EEPROM Control (p. 4-92 in 7870 Databook)* Controls the reading and writing of an external serial 1-bit* EEPROM Device. In order to access the serial EEPROM, you must* first set the SEEMS bit that generates a request to the memory* port for access to the serial EEPROM device. When the memory* port is not busy servicing another request, it reconfigures* to allow access to the serial EEPROM. When this happens, SEERDY* gets set high to verify that the memory port access has been* granted.** After successful arbitration for the memory port, the SEECS bit of* the SEECTL register is connected to the chip select. The SEECK,* SEEDO, and SEEDI are connected to the clock, data out, and data in* lines respectively. The SEERDY bit of SEECTL is useful in that it* gives us an 800 nsec timer. After a write to the SEECTL register,* the SEERDY goes high 800 nsec later. The one exception to this is* when we first request access to the memory port. The SEERDY goes* high to signify that access has been granted and, for this case, has* no implied timing.** See 93cx6.c for detailed information on the protocol necessary to* read the serial EEPROM.*/register SEECTL {address 0x01efield EXTARBACK 0x80field EXTARBREQ 0x40field SEEMS 0x20field SEERDY 0x10field SEECS 0x08field SEECK 0x04field SEEDO 0x02field SEEDI 0x01}/** SCSI Block Control (p. 3-32)* Controls Bus type and channel selection. In a twin channel configuration* addresses 0x00-0x1e are gated to the appropriate channel based on this* register. SELWIDE allows for the coexistence of 8bit and 16bit devices* on a wide bus.*/register SBLKCTL {address 0x01faccess_mode RWfield DIAGLEDEN 0x80 /* Aic78X0 only */field DIAGLEDON 0x40 /* Aic78X0 only */field AUTOFLUSHDIS 0x20field SELBUSB 0x08field ENAB40 0x08 /* LVD transceiver active */field ENAB20 0x04 /* SE/HVD transceiver active */field SELWIDE 0x02field XCVR 0x01 /* External transceiver active */}/** Sequencer Control (p. 3-33)* Error detection mode and speed configuration*/register SEQCTL {address 0x060access_mode RWfield PERRORDIS 0x80field PAUSEDIS 0x40field FAILDIS 0x20field FASTMODE 0x10field BRKADRINTEN 0x08field STEP 0x04field SEQRESET 0x02field LOADRAM 0x01}/** Sequencer RAM Data (p. 3-34)* Single byte window into the Scratch Ram area starting at the address* specified by SEQADDR0 and SEQADDR1. To write a full word, simply write* four bytes in succession. The SEQADDRs will increment after the most* significant byte is written*/register SEQRAM {address 0x061access_mode RW}/** Sequencer Address Registers (p. 3-35)* Only the first bit of SEQADDR1 holds addressing information*/register SEQADDR0 {address 0x062access_mode RW}register SEQADDR1 {address 0x063access_mode RWmask SEQADDR1_MASK 0x01}/** Accumulator* We cheat by passing arguments in the Accumulator up to the kernel driver*/register ACCUM {address 0x064access_mode RWaccumulator}register SINDEX {address 0x065access_mode RWsindex}register DINDEX {address 0x066access_mode RW}register ALLONES {address 0x069access_mode ROallones}register ALLZEROS {address 0x06aaccess_mode ROallzeros}register NONE {address 0x06aaccess_mode WOnone}register FLAGS {address 0x06baccess_mode ROfield ZERO 0x02field CARRY 0x01}register SINDIR {address 0x06caccess_mode RO}register DINDIR {address 0x06daccess_mode WO}register FUNCTION1 {address 0x06eaccess_mode RW}register STACK {address 0x06faccess_mode RO}const STACK_SIZE 4/** Board Control (p. 3-43)*/register BCTL {address 0x084access_mode RWfield ACE 0x08field ENABLE 0x01}/** On the aic78X0 chips, Board Control is replaced by the DSCommand* register (p. 4-64)*/register DSCOMMAND0 {address 0x084access_mode RWfield CACHETHEN 0x80 /* Cache Threshold enable */field DPARCKEN 0x40 /* Data Parity Check Enable */field MPARCKEN 0x20 /* Memory Parity Check Enable */field EXTREQLCK 0x10 /* External Request Lock *//* aic7890/91/96/97 only */field INTSCBRAMSEL 0x08 /* Internal SCB RAM Select */field RAMPS 0x04 /* External SCB RAM Present */field USCBSIZE32 0x02 /* Use 32byte SCB Page Size */field CIOPARCKEN 0x01 /* Internal bus parity error enable */}register DSCOMMAND1 {address 0x085access_mode RWmask DSLATT 0xfc /* PCI latency timer (non-ultra2) */field HADDLDSEL1 0x02 /* Host Address Load Select Bits */field HADDLDSEL0 0x01}/** Bus On/Off Time (p. 3-44) aic7770 only*/register BUSTIME {address 0x085access_mode RWmask BOFF 0xf0mask BON 0x0f}/** Bus Speed (p. 3-45) aic7770 only*/register BUSSPD {address 0x086access_mode RWmask DFTHRSH 0xc0mask STBOFF 0x38mask STBON 0x07mask DFTHRSH_100 0xc0mask DFTHRSH_75 0x80}/* aic7850/55/60/70/80/95 only */register DSPCISTATUS {address 0x086mask DFTHRSH_100 0xc0}/* aic7890/91/96/97 only */register HS_MAILBOX {address 0x086mask HOST_MAILBOX 0xF0mask SEQ_MAILBOX 0x0Fmask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */}const HOST_MAILBOX_SHIFT 4const SEQ_MAILBOX_SHIFT 0/** Host Control (p. 3-47) R/W* Overall host control of the device.*/register HCNTRL {address 0x087access_mode RWfield POWRDN 0x40field SWINT 0x10field IRQMS 0x08field PAUSE 0x04field INTEN 0x02field CHIPRST 0x01field CHIPRSTACK 0x01}/** Host Address (p. 3-48)* This register contains the address of the byte about* to be transferred across the host bus.*/register HADDR {address 0x088size 4access_mode RW}register HCNT {address 0x08csize 3access_mode RW}/** SCB Pointer (p. 3-49)* Gate one of the SCBs into the SCBARRAY window.*/register SCBPTR {address 0x090access_mode RW}/** Interrupt Status (p. 3-50)* Status for system interrupts*/register INTSTAT {address 0x091access_mode RWfield BRKADRINT 0x08field SCSIINT 0x04field CMDCMPLT 0x02field SEQINT 0x01mask BAD_PHASE SEQINT /* unknown scsi bus phase */mask SEND_REJECT 0x10|SEQINT /* sending a message reject */mask PROTO_VIOLATION 0x20|SEQINT /* SCSI protocol violation */mask NO_MATCH 0x30|SEQINT /* no cmd match for reconnect */mask IGN_WIDE_RES 0x40|SEQINT /* Complex IGN Wide Res Msg */mask PDATA_REINIT 0x50|SEQINT /** Returned to data phase* that requires data* transfer pointers to be* recalculated from the* transfer residual.*/mask HOST_MSG_LOOP 0x60|SEQINT /** The bus is ready for the* host to perform another* message transaction. This* mechanism is used for things* like sync/wide negotiation* that require a kernel based* message state engine.*/mask BAD_STATUS 0x70|SEQINT /* Bad status from target */mask PERR_DETECTED 0x80|SEQINT /** Either the phase_lock* or inb_next routine has* noticed a parity error.*/mask DATA_OVERRUN 0x90|SEQINT /** Target attempted to write* beyond the bounds of its* command.*/mask MKMSG_FAILED 0xa0|SEQINT /** Target completed command* without honoring our ATN* request to issue a message.*/mask MISSED_BUSFREE 0xb0|SEQINT /** The sequencer never saw* the bus go free after* either a command complete* or disconnect message.*/mask SCB_MISMATCH 0xc0|SEQINT /** Downloaded SCB's tag does* not match the entry we* intended to download.*/mask NO_FREE_SCB 0xd0|SEQINT /** get_free_or_disc_scb failed.*/mask OUT_OF_RANGE 0xe0|SEQINTmask SEQINT_MASK 0xf0|SEQINT /* SEQINT Status Codes */mask INT_PEND (BRKADRINT|SEQINT|SCSIINT|CMDCMPLT)}/** Hard Error (p. 3-53)* Reporting of catastrophic errors. You usually cannot recover from* these without a full board reset.*/register ERROR {address 0x092access_mode ROfield CIOPARERR 0x80 /* Ultra2 only */field PCIERRSTAT 0x40 /* PCI only */field MPARERR 0x20 /* PCI only */field DPARERR 0x10 /* PCI only */field SQPARERR 0x08field ILLOPCODE 0x04field ILLSADDR 0x02field ILLHADDR 0x01}/** Clear Interrupt Status (p. 3-52)*/register CLRINT {address 0x092access_mode WOfield CLRPARERR 0x10 /* PCI only */field CLRBRKADRINT 0x08field CLRSCSIINT 0x04field CLRCMDINT 0x02field CLRSEQINT 0x01}register DFCNTRL {address 0x093access_mode RWfield PRELOADEN 0x80 /* aic7890 only */field WIDEODD 0x40field SCSIEN 0x20field SDMAEN 0x10field SDMAENACK 0x10field HDMAEN 0x08field HDMAENACK 0x08field DIRECTION 0x04field FIFOFLUSH 0x02field FIFORESET 0x01}register DFSTATUS {address 0x094access_mode ROfield PRELOAD_AVAIL 0x80field DFCACHETH 0x40field FIFOQWDEMP 0x20field MREQPEND 0x10field HDONE 0x08field DFTHRESH 0x04field FIFOFULL 0x02field FIFOEMP 0x01}register DFWADDR {address 0x95access_mode RW}register DFRADDR {address 0x97access_mode RW}register DFDAT {address 0x099access_mode RW}/** SCB Auto Increment (p. 3-59)* Byte offset into the SCB Array and an optional bit to allow auto* incrementing of the address during download and upload operations*/register SCBCNT {address 0x09aaccess_mode RWfield SCBAUTO 0x80mask SCBCNT_MASK 0x1f}/** Queue In FIFO (p. 3-60)* Input queue for queued SCBs (commands that the seqencer has yet to start)*/register QINFIFO {address 0x09baccess_mode RW}/** Queue In Count (p. 3-60)* Number of queued SCBs*/register QINCNT {address 0x09caccess_mode RO}/** Queue Out FIFO (p. 3-61)* Queue of SCBs that have completed and await the host*/register QOUTFIFO {address 0x09daccess_mode WO}register CRCCONTROL1 {address 0x09daccess_mode RWfield CRCONSEEN 0x80field CRCVALCHKEN 0x40field CRCENDCHKEN 0x20field CRCREQCHKEN 0x10field TARGCRCENDEN 0x08field TARGCRCCNTEN 0x04}/** Queue Out Count (p. 3-61)* Number of queued SCBs in the Out FIFO*/register QOUTCNT {address 0x09eaccess_mode RO}register SCSIPHASE {address 0x09eaccess_mode ROfield STATUS_PHASE 0x20field COMMAND_PHASE 0x10field MSG_IN_PHASE 0x08field MSG_OUT_PHASE 0x04field DATA_IN_PHASE 0x02field DATA_OUT_PHASE 0x01mask DATA_PHASE_MASK 0x03}/** Special Function*/register SFUNCT {address 0x09faccess_mode RWfield ALT_MODE 0x80}/** SCB Definition (p. 5-4)*/scb {address 0x0a0size 64SCB_CDB_PTR {size 4alias SCB_RESIDUAL_DATACNTalias SCB_CDB_STORE}SCB_RESIDUAL_SGPTR {size 4}SCB_SCSI_STATUS {size 1}SCB_TARGET_PHASES {size 1}SCB_TARGET_DATA_DIR {size 1}SCB_TARGET_ITAG {size 1}SCB_DATAPTR {size 4}SCB_DATACNT {/** The last byte is really the high address bits for* the data address.*/size 4field SG_LAST_SEG 0x80 /* In the fourth byte */mask SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */}SCB_SGPTR {size 4field SG_RESID_VALID 0x04 /* In the first byte */field SG_FULL_RESID 0x02 /* In the first byte */field SG_LIST_NULL 0x01 /* In the first byte */}SCB_CONTROL {size 1field TARGET_SCB 0x80field STATUS_RCVD 0x80field DISCENB 0x40field TAG_ENB 0x20field MK_MESSAGE 0x10field ULTRAENB 0x08field DISCONNECTED 0x04mask SCB_TAG_TYPE 0x03}SCB_SCSIID {size 1field TWIN_CHNLB 0x80mask TWIN_TID 0x70mask TID 0xf0mask OID 0x0f}SCB_LUN {field SCB_XFERLEN_ODD 0x80mask LID 0x3fsize 1}SCB_TAG {size 1}SCB_CDB_LEN {size 1}SCB_SCSIRATE {size 1}SCB_SCSIOFFSET {size 1}SCB_NEXT {size 1}SCB_64_SPARE {size 16}SCB_64_BTT {size 16}}const SCB_UPLOAD_SIZE 32const SCB_DOWNLOAD_SIZE 32const SCB_DOWNLOAD_SIZE_64 48const SG_SIZEOF 0x08 /* sizeof(struct ahc_dma) *//* --------------------- AHA-2840-only definitions -------------------- */register SEECTL_2840 {address 0x0c0access_mode RWfield CS_2840 0x04field CK_2840 0x02field DO_2840 0x01}register STATUS_2840 {address 0x0c1access_mode RWfield EEPROM_TF 0x80mask BIOS_SEL 0x60mask ADSEL 0x1efield DI_2840 0x01}/* --------------------- AIC-7870-only definitions -------------------- */register CCHADDR {address 0x0E0size 8}register CCHCNT {address 0x0E8}register CCSGRAM {address 0x0E9}register CCSGADDR {address 0x0EA}register CCSGCTL {address 0x0EBfield CCSGDONE 0x80field CCSGEN 0x08field SG_FETCH_NEEDED 0x02 /* Bit used for software state */field CCSGRESET 0x01}register CCSCBCNT {address 0xEF}register CCSCBCTL {address 0x0EEfield CCSCBDONE 0x80field ARRDONE 0x40 /* SCB Array prefetch done */field CCARREN 0x10field CCSCBEN 0x08field CCSCBDIR 0x04field CCSCBRESET 0x01}register CCSCBADDR {address 0x0ED}register CCSCBRAM {address 0xEC}/** SCB bank address (7895/7896/97 only)*/register SCBBADDR {address 0x0F0access_mode RW}register CCSCBPTR {address 0x0F1}register HNSCB_QOFF {address 0x0F4}register SNSCB_QOFF {address 0x0F6}register SDSCB_QOFF {address 0x0F8}register QOFF_CTLSTA {address 0x0FAfield SCB_AVAIL 0x40field SNSCB_ROLLOVER 0x20field SDSCB_ROLLOVER 0x10mask SCB_QSIZE 0x07mask SCB_QSIZE_256 0x06}register DFF_THRSH {address 0x0FBmask WR_DFTHRSH 0x70mask RD_DFTHRSH 0x07mask RD_DFTHRSH_MIN 0x00mask RD_DFTHRSH_25 0x01mask RD_DFTHRSH_50 0x02mask RD_DFTHRSH_63 0x03mask RD_DFTHRSH_75 0x04mask RD_DFTHRSH_85 0x05mask RD_DFTHRSH_90 0x06mask RD_DFTHRSH_MAX 0x07mask WR_DFTHRSH_MIN 0x00mask WR_DFTHRSH_25 0x10mask WR_DFTHRSH_50 0x20mask WR_DFTHRSH_63 0x30mask WR_DFTHRSH_75 0x40mask WR_DFTHRSH_85 0x50mask WR_DFTHRSH_90 0x60mask WR_DFTHRSH_MAX 0x70}register SG_CACHE_PRE {access_mode WOaddress 0x0fcmask SG_ADDR_MASK 0xf8field LAST_SEG 0x02field LAST_SEG_DONE 0x01}register SG_CACHE_SHADOW {access_mode ROaddress 0x0fcmask SG_ADDR_MASK 0xf8field LAST_SEG 0x02field LAST_SEG_DONE 0x01}/* ---------------------- Scratch RAM Offsets ------------------------- *//* These offsets are either to values that are initialized by the board's* BIOS or are specified by the sequencer code.** The host adapter card (at least the BIOS) uses 20-2f for SCSI* device information, 32-33 and 5a-5f as well. As it turns out, the* BIOS trashes 20-2f, writing the synchronous negotiation results* on top of the BIOS values, so we re-use those for our per-target* scratchspace (actually a value that can be copied directly into* SCSIRATE). The kernel driver will enable synchronous negotiation* for all targets that have a value other than 0 in the lower four* bits of the target scratch space. This should work regardless of* whether the bios has been installed.*/scratch_ram {address 0x020size 58/** 1 byte per target starting at this address for configuration values*/BUSY_TARGETS {alias TARG_SCSIRATEsize 16}/** Bit vector of targets that have ULTRA enabled as set by* the BIOS. The Sequencer relies on a per-SCB field to* control whether to enable Ultra transfers or not. During* initialization, we read this field and reuse it for 2* entries in the busy target table.*/ULTRA_ENB {alias CMDSIZE_TABLEsize 2}/** Bit vector of targets that have disconnection disabled as set by* the BIOS. The Sequencer relies in a per-SCB field to control the* disconnect priveldge. During initialization, we read this field* and reuse it for 2 entries in the busy target table.*/DISC_DSB {size 2}CMDSIZE_TABLE_TAIL {size 4}/** Partial transfer past cacheline end to be* transferred using an extra S/G.*/MWI_RESIDUAL {size 1alias TARG_IMMEDIATE_SCB}/** SCBID of the next SCB to be started by the controller.*/NEXT_QUEUED_SCB {size 1}/** Single byte buffer used to designate the type or message* to send to a target.*/MSG_OUT {size 1}/* Parameters for DMA Logic */DMAPARAMS {size 1field PRELOADEN 0x80field WIDEODD 0x40field SCSIEN 0x20field SDMAEN 0x10field SDMAENACK 0x10field HDMAEN 0x08field HDMAENACK 0x08field DIRECTION 0x04 /* Set indicates PCI->SCSI */field FIFOFLUSH 0x02field FIFORESET 0x01}SEQ_FLAGS {size 1field NOT_IDENTIFIED 0x80field NO_CDB_SENT 0x40field TARGET_CMD_IS_TAGGED 0x40field DPHASE 0x20/* Target flags */field TARG_CMD_PENDING 0x10field CMDPHASE_PENDING 0x08field DPHASE_PENDING 0x04field SPHASE_PENDING 0x02field NO_DISCONNECT 0x01}/** Temporary storage for the* target/channel/lun of a* reconnecting target*/SAVED_SCSIID {size 1}SAVED_LUN {size 1}/** The last bus phase as seen by the sequencer.*/LASTPHASE {size 1field CDI 0x80field IOI 0x40field MSGI 0x20mask PHASE_MASK CDI|IOI|MSGImask P_DATAOUT 0x00mask P_DATAIN IOImask P_COMMAND CDImask P_MESGOUT CDI|MSGImask P_STATUS CDI|IOImask P_MESGIN CDI|IOI|MSGImask P_BUSFREE 0x01}/** head of list of SCBs awaiting* selection*/WAITING_SCBH {size 1}/** head of list of SCBs that are* disconnected. Used for SCB* paging.*/DISCONNECTED_SCBH {size 1}/** head of list of SCBs that are* not in use. Used for SCB paging.*/FREE_SCBH {size 1}/** head of list of SCBs that have* completed but have not been* put into the qoutfifo.*/COMPLETE_SCBH {size 1}/** Address of the hardware scb array in the host.*/HSCB_ADDR {size 4}/** Base address of our shared data with the kernel driver in host* memory. This includes the qoutfifo and target mode* incoming command queue.*/SHARED_DATA_ADDR {size 4}KERNEL_QINPOS {size 1}QINPOS {size 1}QOUTPOS {size 1}/** Kernel and sequencer offsets into the queue of* incoming target mode command descriptors. The* queue is full when the KERNEL_TQINPOS == TQINPOS.*/KERNEL_TQINPOS {size 1}TQINPOS {size 1}ARG_1 {size 1mask SEND_MSG 0x80mask SEND_SENSE 0x40mask SEND_REJ 0x20mask MSGOUT_PHASEMIS 0x10mask EXIT_MSG_LOOP 0x08mask CONT_MSG_LOOP 0x04mask CONT_TARG_SESSION 0x02alias RETURN_1}ARG_2 {size 1alias RETURN_2}/** Snapshot of MSG_OUT taken after each message is sent.*/LAST_MSG {size 1}/** Sequences the kernel driver has okayed for us. This allows* the driver to do things like prevent initiator or target* operations.*/SCSISEQ_TEMPLATE {size 1field ENSELO 0x40field ENSELI 0x20field ENRSELI 0x10field ENAUTOATNO 0x08field ENAUTOATNI 0x04field ENAUTOATNP 0x02}}scratch_ram {address 0x056size 4/** These scratch ram locations are initialized by the 274X BIOS.* We reuse them after capturing the BIOS settings during* initialization.*//** The initiator specified tag for this target mode transaction.*/HA_274_BIOSGLOBAL {size 1field HA_274_EXTENDED_TRANS 0x01alias INITIATOR_TAG}SEQ_FLAGS2 {size 1field SCB_DMA 0x01field TARGET_MSG_PENDING 0x02}}scratch_ram {address 0x05asize 6/** These are reserved registers in the card's scratch ram on the 2742.* The EISA configuraiton chip is mapped here. On Rev E. of the* aic7770, the sequencer can use this area for scratch, but the* host cannot directly access these registers. On later chips, this* area can be read and written by both the host and the sequencer.* Even on later chips, many of these locations are initialized by* the BIOS.*/SCSICONF {size 1field TERM_ENB 0x80field RESET_SCSI 0x40field ENSPCHK 0x20mask HSCSIID 0x07 /* our SCSI ID */mask HWSCSIID 0x0f /* our SCSI ID if Wide Bus */}INTDEF {address 0x05csize 1field EDGE_TRIG 0x80mask VECTOR 0x0f}HOSTCONF {address 0x05dsize 1}HA_274_BIOSCTRL {address 0x05fsize 1mask BIOSMODE 0x30mask BIOSDISABLED 0x30field CHANNEL_B_PRIMARY 0x08}}scratch_ram {address 0x070size 16/** Per target SCSI offset values for Ultra2 controllers.*/TARG_OFFSET {size 16}}const TID_SHIFT 4const SCB_LIST_NULL 0xffconst TARGET_CMD_CMPLT 0xfeconst CCSGADDR_MAX 0x80const CCSGRAM_MAXSEGS 16/* WDTR Message values */const BUS_8_BIT 0x00const BUS_16_BIT 0x01const BUS_32_BIT 0x02/* Offset maximums */const MAX_OFFSET_8BIT 0x0fconst MAX_OFFSET_16BIT 0x08const MAX_OFFSET_ULTRA2 0x7fconst MAX_OFFSET 0x7fconst HOST_MSG 0xff/* Target mode command processing constants */const CMD_GROUP_CODE_SHIFT 0x05const STATUS_BUSY 0x08const STATUS_QUEUE_FULL 0x28const TARGET_DATA_IN 1/** Downloaded (kernel inserted) constants*//* Offsets into the SCBID array where different data is stored */const QOUTFIFO_OFFSET downloadconst QINFIFO_OFFSET downloadconst CACHESIZE_MASK downloadconst INVERTED_CACHESIZE_MASK downloadconst SG_PREFETCH_CNT downloadconst SG_PREFETCH_ALIGN_MASK downloadconst SG_PREFETCH_ADDR_MASK download