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// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/CY4_16.v,v 1.1.1.1 2001-11-04 18:59:46 lampret Exp $
 
/*
 
FUNCTION	: Carry modes functions
 
*/
 
`timescale  100 ps / 10 ps
 
`celldefine
 
module CY4_16 (C0, C1, C2, C3, C4, C5, C6, C7);
 
    parameter cds_action = "ignore";
 
    output C0, C1, C2, C3, C4, C5, C6, C7;
 
	supply1 C7;
	supply1 C6;
	supply1 C5;
	supply0 C4;
	supply0 C3;
	supply0 C2;
	supply0 C1;
	supply1 C0;
 
endmodule
 
`endcelldefine