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// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/OFDTXI_24.v,v 1.1.1.1 2001-11-04 18:59:50 lampret Exp $
 
/*
 
FUNCTION	: Output D-FLIP-FLOP with clock enable
 
*/
 
`timescale  100 ps / 10 ps
 
`celldefine
 
module OFDTXI_24 (O, C, CE, D, T);
 
    parameter cds_action = "ignore";
    parameter INIT = 1'b0;
 
    output O;
    reg    o_in;
 
    input  C, CE, D, T;
 
    tri0 GSR = glbl.GSR;
    tri0 GTS = glbl.GTS;
 
	always @(GSR)
	    if (GSR)
		assign o_in = INIT;
	    else
		deassign o_in;
 
	always @(posedge C)
	    if (CE)
		o_in <= D;
 
    or (t_in, GTS, T);
    bufif0 (O, o_in, t_in);
 
    specify
	(posedge C => (O +: D)) = (1, 1);
	(T => O) = (1, 1, 0);
    endspecify
 
endmodule
 
`endcelldefine