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[/] [or1k/] [trunk/] [mp3/] [rtl/] [verilog/] [audio/] [fifo_empty_16.v] - Rev 1778
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`include "timescale.v" module fifo_empty_16 ( DIN, WR_EN, WR_CLK, RD_EN, RD_CLK, AINIT, DOUT, FULL, EMPTY, ALMOST_FULL, ALMOST_EMPTY); input [15 : 0] DIN; input WR_EN; input WR_CLK; input RD_EN; input RD_CLK; input AINIT; output [15 : 0] DOUT; output FULL; output EMPTY; output ALMOST_FULL; output ALMOST_EMPTY; assign DOUT = DIN; assign FULL = 1'b0; assign EMPTY = 1'b0; assign ALMOST_FULL = 1'b0; assign ALMOST_EMPTY = 1'b0; endmodule
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