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[/] [or1k/] [trunk/] [mp3/] [rtl/] [verilog/] [mem_if/] [flash_top.v] - Rev 1778
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////////////////////////////////////////////////////////////////////// //// //// //// MP3 demo Flash interface //// //// //// //// This file is part of the MP3 demo application //// //// http://www.opencores.org/cores/or1k/mp3/ //// //// //// //// Description //// //// Connects MP3 demo tp Flash found on XSV board. //// //// //// //// To Do: //// //// - nothing really //// //// //// //// Author(s): //// //// - Lior Shtram, lior.shtram@flextronicssemi.com //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2001 Authors //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // CVS Revision History // // $Log: not supported by cvs2svn $ // Revision 1.3 2002/01/23 07:50:44 lampret // Added wb_err_o to flash and sram i/f for testing the buserr exception. // // Revision 1.2 2002/01/14 06:18:22 lampret // Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. // // Revision 1.1.1.1 2001/11/04 19:00:09 lampret // First import. // // // synopsys translate_off `include "timescale.v" // synopsys translate_on `include "bench_define.v" `ifdef FLASH_GENERIC module flash_top ( clk, rstn, wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o, flash_rstn, cen, oen, wen, rdy, d, a, a_oe ); input clk; input rstn; input [31:0] wb_dat_i; output [31:0] wb_dat_o; input [31:0] wb_adr_i; input [3:0] wb_sel_i; input wb_we_i; input wb_cyc_i; input wb_stb_i; output wb_ack_o; output wb_err_o; output flash_rstn; output oen; output cen; output wen; input rdy; inout [7:0] d; output [20:0] a; output a_oe; reg [7:0] mem [65535:0]; wire [31:0] adr; `ifdef FLASH_GENERIC_REGISTERED reg wb_ack_o; reg wb_err_o; reg [31:0] wb_dat_o; `endif wire wb_err; assign flash_rstn = 1'b1; assign oen = 1'b1; assign cen = 1'b1; assign wen = 1'b1; assign a = 21'b0; assign a_oe = 1'b1; initial $readmemh("../src/flash.in", mem, 0); assign adr = {wb_adr_i[31:2], 2'b00}; `ifdef FLASH_GENERIC_REGISTERED always @(negedge rstn or posedge clk) if (!rstn) wb_dat_o <= #1 32'h0000_0000; else begin wb_dat_o[7:0] <= #1 wb_adr_i < 65535 ? mem[adr+3] : 8'h00; wb_dat_o[15:8] <= #1 wb_adr_i < 65535 ? mem[adr+2] : 8'h00; wb_dat_o[23:16] <= #1 wb_adr_i < 65535 ? mem[adr+1] : 8'h00; wb_dat_o[31:24] <= #1 wb_adr_i < 65535 ? mem[adr+0] : 8'h00; end `else assign wb_dat_o[7:0] = wb_adr_i < 65535 ? mem[adr+3] : 8'h00; assign wb_dat_o[15:8] = wb_adr_i < 65535 ? mem[adr+2] : 8'h00; assign wb_dat_o[23:16] = wb_adr_i < 65535 ? mem[adr+1] : 8'h00; assign wb_dat_o[31:24] = wb_adr_i < 65535 ? mem[adr+0] : 8'h00; `endif `ifdef FLASH_GENERIC_REGISTERED always @(posedge clk or negedge rstn) if (!rstn) wb_ack_o <= #1 1'b0; else wb_ack_o <= #1 wb_cyc_i & wb_stb_i & !wb_ack_o; `else assign wb_ack_o = wb_cyc_i & wb_stb_i; `endif assign wb_err = wb_cyc_i & wb_stb_i & (|wb_adr_i[27:21]); // If Access to > 2MB (4-bit leading prefix ignored) `ifdef FLASH_GENERIC_REGISTERED always @(posedge clk or negedge rstn) if (!rstn) wb_err_o <= #1 1'b0; else wb_err_o <= #1 wb_err & !wb_err_o; `else assign wb_err_o = wb_err; `endif // synopsys translate_off integer fflash; initial fflash = $fopen("flash.log"); always @(posedge clk) if (wb_cyc_i) if (wb_stb_i & wb_we_i) begin // $fdisplay(fflash, "%t Trying to write into flash at %h (%b)", $time, wb_adr_i, wb_we_i); // #100 $finish; if (wb_sel_i[3]) mem[{wb_adr_i[31:2], 2'b00}+0] = wb_dat_i[31:24]; if (wb_sel_i[2]) mem[{wb_adr_i[31:2], 2'b00}+1] = wb_dat_i[23:16]; if (wb_sel_i[1]) mem[{wb_adr_i[31:2], 2'b00}+2] = wb_dat_i[15:8]; if (wb_sel_i[0]) mem[{wb_adr_i[31:2], 2'b00}+3] = wb_dat_i[7:0]; $fdisplay(fflash, "%t [%h] <- write %h, byte sel %b", $time, wb_adr_i, wb_dat_i, wb_sel_i); end else if (wb_ack_o) $fdisplay(fflash, "%t [%h] -> read %h", $time, wb_adr_i, wb_dat_o); // synopsys translate_on endmodule `else module flash_top ( clk, rstn, wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o, flash_rstn, cen, oen, wen, rdy, d, a, a_oe ); input clk; input rstn; input [31:0] wb_dat_i; output [31:0] wb_dat_o; input [31:0] wb_adr_i; input [3:0] wb_sel_i; input wb_we_i; input wb_cyc_i; input wb_stb_i; output wb_ack_o; output wb_err_o; output flash_rstn; output oen; output cen; output wen; input rdy; inout [7:0] d; output [20:0] a; output a_oe; reg [4:0] counter; reg [31:0] data_sr; reg f_ack; reg [3:0] middle_tphqv; always @(posedge clk or negedge rstn) begin if(!rstn) counter <= #1 5'h0; else if(!wb_cyc_i | (counter == 5'h10) | (|middle_tphqv)) counter <= #1 5'h0; else counter <= #1 counter + 1; end always @(posedge clk or negedge rstn) begin if(!rstn) f_ack <= #1 1'h0; else if(counter == 5'h0f && !(|middle_tphqv)) f_ack <= #1 1'h1; else f_ack <= #1 1'h0; end assign wb_ack_o = f_ack; assign flash_rstn = rstn; assign a = { ~wb_adr_i[20], wb_adr_i[19:2], counter[3:2] }; assign a_oe = (wb_cyc_i &! (|middle_tphqv)); assign wb_dat_o = data_sr; assign oen = |middle_tphqv; assign wen = 1'b1; /* SIMON */ //assign cen = |middle_tphqv | (counter[1:0] == 2'b01); assign cen = |middle_tphqv | (counter[1:0] == 2'b01) | (counter[4:0] == 5'b0); assign wb_err_o = 1'b0; // synopsys translate_off integer fflash; initial fflash = $fopen("flash.log"); always @(posedge clk) if (wb_cyc_i & !(|middle_tphqv)) begin // wb_ack_o should be qualified with wb_stb_i as well however OR1200 doesn't do this currently if (wb_stb_i & wb_we_i) begin // $fdisplay(fflash, "%t Trying to write into flash at %h", $time, wb_adr_i); // #100 $finish; end else if (wb_ack_o) $fdisplay(fflash, "%t [%h] -> read %h", $time, wb_adr_i, wb_dat_o); end // synopsys translate_on always @(posedge clk or negedge rstn) if (!rstn) middle_tphqv <= #1 4'hf; else if (middle_tphqv) middle_tphqv <= #1 middle_tphqv - 1; always @(posedge clk or negedge rstn) begin if (!rstn) data_sr <= #1 32'b0; else if (counter[1:0] == 2'h3) begin case (counter[3:2]) 2'h0 : data_sr[31:24] <= #1 d; 2'h1 : data_sr[23:16] <= #1 d; 2'h2 : data_sr[15:8] <= #1 d; 2'h3 : data_sr[7:0] <= #1 d; default : data_sr <= #1 32'bx; endcase end end endmodule `endif
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