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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Debug Unit                                         ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Basic OR1200 debug unit.                                    ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
//
// Debug unit
//
 
module du(
	// RISC Internal Interface
	clk, rst,
	dclsu_lsuop, icfetch_op, ex_freeze, branch_op,
	du_stall, du_addr, du_dat_i, du_dat_o, du_read, du_write, du_except,
	spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
 
	// External Debug Interface
	dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,
	dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o
);
 
parameter dw = `OPERAND_WIDTH;
parameter aw = `OPERAND_WIDTH;
 
//
// I/O
//
 
//
// RISC Internal Interface
//
input				clk;		// Clock
input				rst;		// Reset
input	[`LSUOP_WIDTH-1:0]	dclsu_lsuop;	// LSU status
input	[`FETCHOP_WIDTH-1:0]	icfetch_op;	// IFETCH unit status
input				ex_freeze;	// EX stage freeze
input	[`BRANCHOP_WIDTH-1:0]	branch_op;	// Branch op
output				du_stall;	// Debug Unit Stall
output	[aw-1:0]		du_addr;	// Debug Unit Address
input	[dw-1:0]		du_dat_i;	// Debug Unit Data In
output	[dw-1:0]		du_dat_o;	// Debug Unit Data Out
output				du_read;	// Debug Unit Read Enable
output				du_write;	// Debug Unit Write Enable
input	[`EXCEPT_WIDTH-1:0]	du_except;	// Exception started
input				spr_cs;		// SPR Chip Select
input				spr_write;	// SPR Read/Write
input	[aw-1:0]		spr_addr;	// SPR Address
input	[dw-1:0]		spr_dat_i;	// SPR Data Input
output	[dw-1:0]		spr_dat_o;	// SPR Data Output
 
//
// External Debug Interface
//
input				dbg_stall_i;	// External Stall Input
input	[dw-1:0]		dbg_dat_i;	// External Data Input
input	[aw-1:0]		dbg_adr_i;	// External Address Input
input	[2:0]			dbg_op_i;	// External Operation Select Input
input				dbg_ewt_i;	// External Watchpoint Trigger Input
output	[3:0]			dbg_lss_o;	// External Load/Store Unit Status
output	[1:0]			dbg_is_o;	// External Insn Fetch Status
output	[10:0]			dbg_wp_o;	// Watchpoints Outputs
output				dbg_bp_o;	// Breakpoint Output
output	[dw-1:0]		dbg_dat_o;	// External Data Output
 
 
//
// Some connections go directly from the CPU through DU to Debug I/F
//
assign dbg_lss_o = dclsu_lsuop;
assign dbg_is_o = icfetch_op;
assign dbg_wp_o = 11'b000_0000_0000;
assign dbg_dat_o = du_dat_i;
 
//
// Some connections go directly from Debug I/F through DU to the CPU
//
assign du_stall = dbg_stall_i;
assign du_addr = dbg_adr_i;
assign du_dat_o = dbg_dat_i;
assign du_read = (dbg_op_i == `DU_OP_READSPR);
assign du_write = (dbg_op_i == `DU_OP_WRITESPR);
 
`ifdef DU_IMPLEMENTED
 
//
// Debug Mode Register 1 (only ST and BT implemented)
//
`ifdef DU_DMR1
reg	[23:22]			dmr1;		// DMR1 implemented (ST & BT)
`else
wire	[23:22]			dmr1;		// DMR1 not implemented
`endif
 
//
// Debug Mode Register 2 (not implemented)
//
`ifdef DU_DMR2
wire	[31:0]			dmr2;		// DMR not implemented
`endif
 
//
// Debug Stop Register
//
`ifdef DU_DSR
reg	[13:0]			dsr;		// DSR implemented
`else
wire	[13:0]			dsr;		// DSR not implemented
`endif
 
//
// Debug Reason Register
//
`ifdef DU_DRR
reg	[13:0]			drr;		// DRR implemented
reg	[13:0]			except_unmasked;
`else
wire	[13:0]			drr;		// DRR not implemented
`endif
 
//
// Internal wires
//
wire	[13:0]			except_masked;
wire				dmr1_sel; 	// DMR1 select
wire				dsr_sel; 	// DSR select
wire				drr_sel; 	// DRR select
reg				dbg_bp_r;
`ifdef DU_READREGS
reg	[31:0]			spr_dat_o;
`endif
 
//
// DU registers address decoder
//
`ifdef DU_DMR1
assign dmr1_sel = (spr_cs && (spr_addr[`SPROFS_BITS] == `DU_OFS_DMR1));
`endif
`ifdef DU_DSR
assign dsr_sel = (spr_cs && (spr_addr[`SPROFS_BITS] == `DU_OFS_DSR));
`endif
`ifdef DU_DRR
assign drr_sel = (spr_cs && (spr_addr[`SPROFS_BITS] == `DU_OFS_DRR));
`endif
 
//
// Decode started exception
//
always @(du_except)
	case (du_except)
		4'he: except_unmasked = 14'b10_0000_0000_0000;
		4'hd: except_unmasked = 14'b01_0000_0000_0000;
		4'hc: except_unmasked = 14'b00_1000_0000_0000;
		4'hb: except_unmasked = 14'b00_0100_0000_0000;
		4'ha: except_unmasked = 14'b00_0010_0000_0000;
		4'h9: except_unmasked = 14'b00_0001_0000_0000;
		4'h8: except_unmasked = 14'b00_0000_1000_0000;
		4'h7: except_unmasked = 14'b00_0000_0100_0000;
		4'h6: except_unmasked = 14'b00_0000_0010_0000;
		4'h5: except_unmasked = 14'b00_0000_0001_0000;
		4'h4: except_unmasked = 14'b00_0000_0000_1000;
		4'h3: except_unmasked = 14'b00_0000_0000_0100;
		4'h2: except_unmasked = 14'b00_0000_0000_0010;
		4'h1: except_unmasked = 14'b00_0000_0000_0001;
		default: except_unmasked = 14'b00_0000_0000_0000;
	endcase
 
//
// Get only 'stop' exceptions
//
assign except_masked = dsr & except_unmasked;
 
//
// dbg_bp_o is registered
//
assign dbg_bp_o = dbg_bp_r;
 
//
// Breakpoint activation register
//
always @(posedge clk or posedge rst)
	if (rst)
		dbg_bp_r <= #1 1'b0;
	else
		dbg_bp_r <= |except_masked
`ifdef DU_DMR1_ST
			| ~ex_freeze & dmr1[`DU_DMR1_ST]
`endif
`ifdef DU_DMR1_BT
			| ~ex_freeze & (branch_op != `BRANCHOP_NOP) & dmr1[`DU_DMR1_BT]
`endif
			;
 
//
// Write to DMR1
//
`ifdef DU_DMR1
always @(posedge clk or posedge rst)
	if (rst)
		dmr1 <= 2'b00;
	else if (dmr1_sel && spr_write)
		dmr1 <= #1 spr_dat_i[23:22];
`else
assign dmr1 = 2'b00;
`endif
 
//
// DMR2 bits tied to zero
//
`ifdef DU_DMR2
assign dmr2 = 32'h0000_0000;
`endif
 
//
// Write to DSR
//
`ifdef DU_DSR
always @(posedge clk or posedge rst)
	if (rst)
		dsr <= 14'b0;
	else if (dsr_sel && spr_write)
		dsr <= #1 spr_dat_i[13:0];
`else
assign dsr = 14'b0;
`endif
 
//
// Write to DRR
//
`ifdef DU_DRR
always @(posedge clk or posedge rst)
	if (rst)
		drr <= 14'b0;
	else if (drr_sel && spr_write)
		drr <= #1 spr_dat_i[13:0];
	else
		drr <= #1 drr | except_masked;
`else
assign drr = 14'b0;
`endif
 
//
// Read DU registers
//
`ifdef DU_READREGS
always @(spr_addr or dsr or drr)
	case (spr_addr[`SPROFS_BITS])
`ifdef DU_DMR1
		`DU_OFS_DMR1:
			spr_dat_o = {8'b0, dmr1, 22'b0};
`endif
`ifdef DU_DMR2
		`DU_OFS_DMR2:
			spr_dat_o = dmr2;
`endif
`ifdef DU_DSR
		`DU_OFS_DSR:
			spr_dat_o = {18'b0, dsr};
`endif
`ifdef DU_DRR
		`DU_OFS_DRR:
			spr_dat_o = {18'b0, drr};
`endif
		default:
			spr_dat_o = 32'h0000_0000;
	endcase
`endif
 
`else
 
//
// When DU is not implemented, drive all outputs as would when DU is disabled
//
assign dbg_bp_o = 1'b0;
 
//
// Read DU registers
//
`ifdef DU_READREGS
assign spr_dat_o = 32'h0000_0000;
`ifdef DU_UNUSED_ZERO
`endif
`endif
 
`endif
 
endmodule