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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  MP3 demo Top Level                                          ////
////                                                              ////
////  This file is part of the MP3 demo application               ////
////  http://www.opencores.org/cores/or1k/mp3/                    ////
////                                                              ////
////  Description                                                 ////
////  Top level instantiating all the blocks.                     ////
////                                                              ////
////  To Do:                                                      ////
////   - nothing really                                           ////
////                                                              ////
////  Author(s):                                                  ////
////      - Lior Shtram, lior.shtram@flextronicssemi.com          ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2001/11/04 19:00:08  lampret
// First import.
//
 
`define EXCLUDE_DBG
// `define EXCLUDE_VGA
// `define EXCLUDE_RISC
// `define VGA_RAMDAC
 
`include "xfpga_defines.v"
 
module xfpga_top (
 
// Global connections
	clk,
	clk2,
	rstn,
 
// Flash RAM
	flash_rstn,
	flash_cen,
	flash_oen,
	flash_wen,
	flash_rdy,
	flash_d,
	flash_a,
 
// SRAM Right
	sram_r_cen,
	sram_r_oen,
	sram_r0_wen,
        sram_r1_wen, 
	sram_r_d,
	sram_r_a,
 
// SRAM Left
	sram_l_cen,
	sram_l_oen,
	sram_l0_wen,
        sram_l1_wen,
	sram_l_d,
	sram_l_a,
 
`ifdef VGA_RAMDAC
 
// VGA RAMDAC
	ramdac_pixclk,
	ramdac_hsyncn,
	ramdac_vsync,
	ramdac_blank,
	ramdac_p,
	ramdac_rdn,
	ramdac_wrn,
	ramdac_rs,
	ramdac_d,
 
`else
 
// VGA Direct
	vga_blank,
	vga_pclk,
	vga_hsyncn,
	vga_vsyncn,
	vga_r,
	vga_g,
	vga_b,
 
`endif
 
// Codec connections
	codec_mclk,
	codec_lrclk,
	codec_sclk,
	codec_sdin,
	codec_sdout,
 
// Ethernet
	eth_col,
	eth_crs,
	eth_trste,
	eth_tx_clk,
	eth_tx_en,
	eth_tx_er,
	eth_txd,
	eth_rx_clk,
	eth_rx_dv,
	eth_rx_er,
	eth_rxd,
	eth_fds_mdint,
	eth_mdc,
	eth_mdio,
 
// Switches
	sw,
 
// Used for tracing fifo activity (CODEC)
  USB_VPO,
  USB_VMO,
 
// PS2 port
	ps2_clk,
	ps2_data,
 
// GDB JTAG CPLD
/*
cpld_muxr,
	cpld_muxd,
*/
	cpld_tdo
 
);
 
 
// Global connections
 
input clk;
input clk2;
input rstn;
 
// Flash RAM
 
output 		flash_rstn;
output 		flash_cen;
output 		flash_oen;
output 		flash_wen;
input 		flash_rdy;
inout [7:0]	flash_d;
inout [20:0]	flash_a;
 
// SRAM Right
 
output		sram_r_cen;
output		sram_r1_wen;
output		sram_r0_wen;
output		sram_r_oen;
output [18:0]	sram_r_a;
inout [15:0]	sram_r_d;
 
// SRAM Left
 
output		sram_l_cen;
output		sram_l0_wen;
output		sram_l1_wen;
output		sram_l_oen;
output [18:0]	sram_l_a;
inout [15:0]	sram_l_d;
 
`ifdef VGA_RAMDAC
 
output 		ramdac_pixclk;
output		ramdac_hsyncn;
output		ramdac_vsync;
output		ramdac_blank;
output [7:0]	ramdac_p;
output		ramdac_rdn;
output		ramdac_wrn;
output [2:0]	ramdac_rs;
inout  [7:0]	ramdac_d;
 
`else
 
// VGA Direct
 
output		vga_pclk;
output		vga_blank;
output		vga_hsyncn;
output		vga_vsyncn;
output [3:0]	vga_r;
output [3:0]	vga_g;
output [3:0]	vga_b;
 
`endif
 
// Stereo Codec
 
output		codec_mclk;
output		codec_lrclk;
output		codec_sclk;
output		codec_sdin;
input		codec_sdout;
 
// Ethernet
 
output		eth_tx_er;
input		eth_tx_clk;
output		eth_tx_en;
output [4:0]	eth_txd;
input		eth_rx_er;
input		eth_rx_clk;
input		eth_rx_dv;
input [4:0]	eth_rxd;
input		eth_col;
input		eth_crs;
output		eth_trste;
input		eth_fds_mdint;
inout		eth_mdio;
output		eth_mdc;
 
// Switches
input [2:1]	sw;
 
// Used for tracing fifo activity (CODEC)
output USB_VPO;
output USB_VMO;
 
// PS2 port
inout		ps2_clk;
inout		ps2_data;
 
// GDB JTAG muxed from the CPLD
/*
input		cpld_muxr;
input		cpld_muxd;
*/
output		cpld_tdo;
 
/////////////////////////////////////////////////////////////////////////////////////
// And now for the insides
 
wire [31:0]	wb_vs_adr_i;
wire [31:0]	wb_vs_dat_i;
wire [31:0]	wb_vs_dat_o;
wire [3:0]	wb_vs_sel_i;
wire 		wb_vs_we_i;
wire 		wb_vs_stb_i;
wire 		wb_vs_cyc_i;
wire 		wb_vs_ack_o;
wire 		wb_vs_err_o;
 
wire [31:0]	wb_vm_adr_o;
wire [31:0] 	wb_vm_dat_i;
wire [3:0]	wb_vm_sel_o;
wire		wb_vm_we_o;
wire 		wb_vm_stb_o;
wire		wb_vm_cyc_o;
wire		wb_vm_cab_o;
wire		wb_vm_ack_i;
wire		wb_vm_err_i;
 
wire [31:0]	wb_dm_adr_o;
wire [31:0] 	wb_dm_dat_i;
wire [31:0] 	wb_dm_dat_o;
wire [3:0]	wb_dm_sel_o;
wire		wb_dm_we_o;
wire 		wb_dm_stb_o;
wire		wb_dm_cyc_o;
wire		wb_dm_cab_o;
wire		wb_dm_ack_i;
wire		wb_dm_err_i;
 
wire [31:0]	wb_ri_adr_o;
wire		wb_ri_cyc_o;
wire [31:0]	wb_ri_dat_i;
wire [31:0]	wb_ri_dat_o;
wire [3:0]	wb_ri_sel_o;
wire		wb_ri_ack_i;
wire		wb_ri_err_i;
wire		wb_ri_rty_i;
wire		wb_ri_we_o;
wire		wb_ri_stb_o;
 
wire [31:0]	wb_rd_adr_o;
wire		wb_rd_cyc_o;
wire [31:0]	wb_rd_dat_i;
wire [31:0]	wb_rd_dat_o;
wire [3:0]	wb_rd_sel_o;
wire		wb_rd_ack_i;
wire		wb_rd_err_i;
wire		wb_rd_rty_i;
wire		wb_rd_we_o;
wire		wb_rd_stb_o;
 
wire [31:0]	wb_sr_dat_i;
wire [31:0]	wb_sr_dat_o;
wire [31:0]	wb_sr_adr_i;
wire [3:0]	wb_sr_sel_i;
wire		wb_sr_we_i;
wire		wb_sr_cyc_i;
wire		wb_sr_stb_i;
wire		wb_sr_ack_o;
wire		wb_sr_err_o;
 
wire [31:0]	wb_fl_dat_i;
wire [31:0]	wb_fl_dat_o;
wire [31:0]	wb_fl_adr_i;
wire [3:0]	wb_fl_sel_i;
wire		wb_fl_we_i;
wire		wb_fl_cyc_i;
wire		wb_fl_stb_i;
wire		wb_fl_ack_o;
wire		wb_fl_err_o;
 
wire [31:0]	wb_au_dat_i;
wire [31:0]	wb_au_dat_o;
wire [31:0]	wb_au_adr_i;
wire [3:0]	wb_au_sel_i;
wire		wb_au_we_i;
wire		wb_au_cyc_i;
wire		wb_au_stb_i;
wire		wb_au_ack_o;
wire		wb_au_err_o;
 
wire		vga_int;
 
wire		audio_dreq;
 
reg my_int;
 
wire [3:0]	vga_r_int;
wire [3:0]	vga_g_int;
wire [3:0]	vga_b_int;
 
wire crt_hsync;
wire crt_vsync;
 
wire	[3:0]	dbg_lss;
wire	[1:0]	dbg_is;
wire	[10:0]	dbg_wp;
wire		dbg_bp;
wire	[31:0]	dbg_dat_dbg;
wire	[31:0]	dbg_dat_risc;
wire	[31:0]	dbg_adr;
wire		dbg_ewt;
wire		dbg_stall;
wire	[2:0]	dbg_op;
 
wire		jtag_tdi;
wire		jtag_tms;
wire		jtag_tck;
wire		jtag_trst;
wire		jtag_tdo;
 
wire	[20:0]	flash_a_int;
wire			flash_a_oe;
 
wire simon = sw[1];
wire igor  = sw[2];
 
 
reg resetn_d;
reg resetn;
wire	wb_clk_i;
wire	clk_dll;
wire	clk_buf1;
 
`ifdef EXCLUDE_DBG
`else
reg sram_ra;
`endif
 
always @ (posedge wb_clk_i or negedge rstn)
begin
  if(~rstn)
    resetn_d <= 1'b0;
  else
    resetn_d <= #1 1'b1;
end
 
always @ (posedge wb_clk_i)
begin
  resetn <= #1 resetn_d;
end
 
`ifdef TARGET_VIRTEX
IBUFG IBUFG1(.O(wb_clk_i), .I(clk));
`else
assign wb_clk_i = clk;
`endif
 
/////////////////////////////////////////////////////////////////////////////////////
// GDB JTAG demultiplexer
`ifdef EXCLUDE_DBG
assign jtag_tms  = 1'b0;
assign jtag_tdi  = 1'b0;
assign jtag_trst = 1'b1;
assign jtag_tck  = 1'b0;
assign cpld_tdo  = 1'b0;
 
assign flash_a = flash_a_int;
`else
/* SIMON */
 
always @ (posedge clk or negedge rstn)
begin
  if(~rstn)
    sram_ra <= 1'b0;
  else if(wb_sr_cyc_i & wb_sr_stb_i & !wb_sr_we_i & !sram_ra)
    sram_ra <= #1 1'b1;
end
assign jtag_tms = ~sram_ra ? 1'b0 : flash_a[6];
assign jtag_tdi = ~sram_ra ? 1'b0 : flash_a[7];
assign jtag_trst = ~sram_ra ? 1'b1 : flash_a[8];
assign jtag_tck = ~sram_ra ? 1'b0 : flash_a[9];
assign cpld_tdo = ~sram_ra ? 1'b0 : jtag_tdo;
 
assign flash_a = ~sram_ra ? flash_a_int : 21'bz;
`endif
 
/////////////////////////////////////////////////////////////////////////////////////
// The VGA block
 
`ifdef EXCLUDE_VGA
   initial $display("Warning: exclude vga.");
   vga_dummy_top vga 
   (
  	.wb_clk_i( wb_clk_i ),
  	.wb_rst_i( resetn ),
  	.rst_nreset_i( resetn ),
  	.wb_inta_o( vga_int ),
  	.clk_pclk_i( vga_pclk ),
  	.vga_hsync_pad_o( vga_hsyncn ),
  	.vga_vsync_pad_o( vga_vsyncn ),
  	.vga_csync_pad_o( ),
  	.vga_blank_pad_o( vga_blank ),
  	.vga_r_pad_o( vga_r[3:0] ),
  	.vga_b_pad_o( vga_b[3:0] ),
  	.vga_g_pad_o( vga_g[3:0] ),
 
  	.wb_adr_i( wb_vs_adr_i ),
  	.wb_sdat_i( wb_vs_dat_i ),
  	.wb_sdat_o( wb_vs_dat_o ),
  	.wb_sel_i( wb_vs_sel_i ),
  	.wb_we_i( wb_vs_we_i ),
  	.wb_vga_stb_i( wb_vs_stb_i ),
  	.wb_clut_stb_i( wb_vs_stb_i ),
  	.wb_cyc_i( wb_vs_cyc_i ),
  	.wb_ack_o( wb_vs_ack_o ),
  	.wb_err_o( wb_vs_err_o ),
 
  	.wb_adr_o( wb_vm_adr_o ),
  	.wb_mdat_i( wb_vm_dat_i ),
  	.wb_sel_o( wb_vm_sel_o ),
  	.wb_we_o( wb_vm_we_o ),
  	.wb_stb_o( wb_vm_stb_o ),
  	.wb_cyc_o( wb_vm_cyc_o ),
  	.wb_cab_o( wb_vm_cab_o ),
  	.wb_ack_i( wb_vm_ack_i ),
  	.wb_err_i( wb_vm_err_i )
   );
`else
 
 
 
 
   // CRT controler instance
   ssvga_top CRT
   (
    // Clock and reset
    .wb_clk_i(wb_clk_i), 
    .wb_rst_i(~resetn),
 
    // WISHBONE Master I/F
    .wbm_cyc_o  (wb_vm_cyc_o), 
    .wbm_stb_o  (wb_vm_stb_o), 
    .wbm_sel_o  (wb_vm_sel_o), 
    .wbm_we_o   (wb_vm_we_o),
    .wbm_adr_o  (wb_vm_adr_o), 
    .wbm_dat_o  (), 
    .wbm_cab_o  (wb_vm_cab_o),
    .wbm_dat_i  (wb_vm_dat_i), 
    .wbm_ack_i  (wb_vm_ack_i), 
    .wbm_err_i  (wb_vm_err_i), 
    .wbm_rty_i  (1'b0),
 
    // WISHBONE Slave I/F
    .wbs_cyc_i  (wb_vs_cyc_i), 
    .wbs_stb_i  (wb_vs_stb_i), 
    .wbs_sel_i  (wb_vs_sel_i), 
    .wbs_we_i   (wb_vs_we_i),
    .wbs_adr_i  (wb_vs_adr_i), 
    .wbs_dat_i  (wb_vs_dat_i), 
    .wbs_cab_i  (1'b0),
    .wbs_dat_o  (wb_vs_dat_o), 
    .wbs_ack_o  (wb_vs_ack_o), 
    .wbs_err_o  (wb_vs_err_o), 
    .wbs_rty_o  (),
 
    // Signals to VGA display
    .pad_hsync_o (crt_hsync), 
    .pad_vsync_o (crt_vsync), 
    .pad_rgb_o   ({vga_r_int, vga_g_int, vga_b_int}),
    .led_o       (),
	.pix_clk     (crt_out_reg_clk),
	.misc({11'b0, jtag_tdo, jtag_trst, jtag_tdi, jtag_tms, jtag_tck})
   );
 
   CRTC_IOB crt_out_reg
   (
    .reset_in     (~resetn),
    .clk_in       (crt_out_reg_clk),
    .hsync_in     (crt_hsync),
    .vsync_in     (crt_vsync),
    .rgb_in       ({vga_r_int, vga_g_int, vga_b_int}),
    .hsync_out    (vga_hsyncn),
    .vsync_out    (vga_vsyncn),
    .rgb_out      ({vga_r, vga_g, vga_b})
   ) ;
`endif
 
 
/////////////////////////////////////////////////////////////////////////////////////
// The Audio block
//
audio_top audio (
	.clk( wb_clk_i ),
	.rstn( resetn ),
	.wb_dat_i( wb_au_dat_i ),
	.wb_dat_o( wb_au_dat_o ),
	.wb_adr_i( wb_au_adr_i ),
	.wb_sel_i( wb_au_sel_i ),
	.wb_we_i(  wb_au_we_i  ),
	.wb_cyc_i( wb_au_cyc_i ),
	.wb_stb_i( wb_au_stb_i ),
	.wb_ack_o( wb_au_ack_o ),
	.wb_err_o( wb_au_err_o ),
	.mclk( codec_mclk ),
	.lrclk( codec_lrclk ),
	.sclk( codec_sclk ),
	.sdin( codec_sdin ),
	.sdout( codec_sdout ),
 
	.audio_dreq( audio_dreq ), 
	.igor(simon),
	.simon(igor),
	.USB_VPO(USB_VPO),
  .USB_VMO(USB_VMO)
 
);
 
//////////////////////////////////////////////////////
// Development i/f
//`define DBG_IF_MODEL
`ifdef DBG_IF_MODEL
dbg_if_model dbg1  (
	.tms_pad_i(jtag_tms),
	.tck_pad_i(jtag_tck),
	.trst_pad_i(jtag_trst),
  .tdi_pad_i(jtag_tdi),
	.tdo_pad_o(jtag_tdo), 
 
  .capture_dr_o(), 
  .shift_dr_o(), 
  .update_dr_o(), 
  .extest_selected_o(), 
  .bs_chain_i(1'b0),
 
	.wb_rst_i(~resetn),
	.risc_clk_i(wb_clk_i),
  .risc_data_i(dbg_dat_risc),
	.wp_i(dbg_wp),
	.bp_i(dbg_bp),
	.lsstatus_i(dbg_lss),
	.istatus_i(dbg_is),
 
	.risc_data_o(dbg_dat_dbg),
	.risc_addr_o(dbg_adr),
	.opselect_o(dbg_op),
	.risc_stall_o(dbg_stall),
	.reset_o(),
 
	.wb_clk_i(wb_clk_i),
	.wb_adr_o( wb_dm_adr_o ),
	.wb_dat_i( wb_dm_dat_i ),
	.wb_dat_o( wb_dm_dat_o ),
	.wb_sel_o( wb_dm_sel_o ),
	.wb_we_o(  wb_dm_we_o  ),
	.wb_stb_o( wb_dm_stb_o ),
	.wb_cyc_o( wb_dm_cyc_o ),
	.wb_cab_o( wb_dm_cab_o ),
	.wb_ack_i( wb_dm_ack_i ),
	.wb_err_i( wb_dm_err_i )
);
`else
dbg_top dbg1  (
/*
	.tms_pad_i(1'b0),
	.tck_pad_i(1'b0),
	.trst_pad_i(1'b1),
  .tdi_pad_i(1'b0),
	.tdo_pad_o(), 
*/
	.tms_pad_i(jtag_tms),
	.tck_pad_i(jtag_tck),
	.trst_pad_i(jtag_trst),
  .tdi_pad_i(jtag_tdi),
	.tdo_pad_o(jtag_tdo), 
 
  .capture_dr_o(), 
  .shift_dr_o(), 
  .update_dr_o(), 
  .extest_selected_o(), 
  .bs_chain_i(1'b0),
 
	.wb_rst_i(~resetn),
	.risc_clk_i(wb_clk_i),
  .risc_data_i(dbg_dat_risc),
	.wp_i(dbg_wp),
	.bp_i(dbg_bp),
	.lsstatus_i(dbg_lss),
	.istatus_i(dbg_is),
 
	.risc_data_o(dbg_dat_dbg),
	.risc_addr_o(dbg_adr),
	.opselect_o(dbg_op),
	.risc_stall_o(dbg_stall),
	.reset_o(),
 
	.wb_clk_i(wb_clk_i),
	.wb_adr_o( wb_dm_adr_o ),
	.wb_dat_i( wb_dm_dat_i ),
	.wb_dat_o( wb_dm_dat_o ),
	.wb_sel_o( wb_dm_sel_o ),
	.wb_we_o(  wb_dm_we_o  ),
	.wb_stb_o( wb_dm_stb_o ),
	.wb_cyc_o( wb_dm_cyc_o ),
	.wb_cab_o( wb_dm_cab_o ),
	.wb_ack_i( wb_dm_ack_i ),
	.wb_err_i( wb_dm_err_i )
);
`endif
 
/////////////////////////////////////////////////////////////////////////////////////
// The CPU block
`ifdef EXCLUDE_RISC
or1200_dummy risc (
`else
or1200_top risc (
`endif
	.iwb_clk_i( wb_clk_i ),
	.iwb_rst_i( ~resetn ),
	.iwb_cyc_o( wb_ri_cyc_o ),
	.iwb_adr_o( wb_ri_adr_o ),
	.iwb_dat_i( wb_ri_dat_i ),
	.iwb_dat_o( wb_ri_dat_o ),
	.iwb_sel_o( wb_ri_sel_o ),
	.iwb_ack_i( wb_ri_ack_i ),
	.iwb_err_i( wb_ri_err_i ),
	.iwb_rty_i( wb_ri_rty_i ),
	.iwb_we_o(  wb_ri_we_o  ),
	.iwb_stb_o( wb_ri_stb_o ),
	.iwb_cab_o(		),
 
	.dwb_clk_i( wb_clk_i ),
	.dwb_rst_i( ~resetn ),
	.dwb_cyc_o( wb_rd_cyc_o ),
	.dwb_adr_o( wb_rd_adr_o ),
	.dwb_dat_i( wb_rd_dat_i ),
	.dwb_dat_o( wb_rd_dat_o ),
	.dwb_sel_o( wb_rd_sel_o ),
	.dwb_ack_i( wb_rd_ack_i ),
	.dwb_err_i( wb_rd_err_i ),
	.dwb_rty_i( wb_rd_rty_i ),
	.dwb_we_o(  wb_rd_we_o  ),
	.dwb_stb_o( wb_rd_stb_o ),
 
	.rst_i( ~resetn ),
	.clk_i( clk2 ),
`ifdef OR1200_CLMODE_1TO2
	.clmode_i( 2'b01 ),
`else
`ifdef OR1200_CLMODE_1TO4
	.clmode_i( 2'b11 ),
`else
	.clmode_i( 2'b00 ),
`endif
`endif
	.dbg_stall_i(dbg_stall),
	.dbg_dat_i(dbg_dat_dbg),
	.dbg_adr_i(dbg_adr),
	.dbg_op_i(dbg_op),
	.dbg_ewt_i(1'b0),
 
	.dbg_lss_o(dbg_lss),
	.dbg_is_o(dbg_is),
	.dbg_wp_o(dbg_wp),
	.dbg_bp_o(dbg_bp),
	.dbg_dat_o(dbg_dat_risc),
 
	.pm_clksd_o( ),
	.pm_cpustall_i( 1'b0 ),
	.pm_dc_gate_o( ),
	.pm_ic_gate_o( ),
	.pm_dmmu_gate_o( ),
	.pm_immu_gate_o( ),
	.pm_tt_gate_o( ),
	.pm_cpu_gate_o( ),
	.pm_wakeup_o( ),
	.pm_lvolt_o( ),
//	.pic_ints_i( { 19'b0, audio_dreq } )
	.pic_ints_i( { my_int, 19'b0} )
);
 
/////////////////////////////////////////////////////////////////////////////////////
// The Flash controller
flash_top flash (
	.clk( wb_clk_i ),
	.rstn( resetn ),
	.wb_dat_i( wb_fl_dat_i ),
	.wb_dat_o( wb_fl_dat_o ),
	.wb_adr_i( wb_fl_adr_i ),
	.wb_sel_i( wb_fl_sel_i ),
	.wb_we_i(  wb_fl_we_i  ),
	.wb_cyc_i( wb_fl_cyc_i ),
	.wb_stb_i( wb_fl_stb_i ),
	.wb_ack_o( wb_fl_ack_o ),
	.wb_err_o( wb_fl_err_o ),
	.flash_rstn( flash_rstn ),
	.cen( flash_cen ),
	.oen( flash_oen ),
	.wen( flash_wen ),
	.rdy( flash_rdy ),
	.d( flash_d ),
	.a( flash_a_int ),
	.a_oe( flash_a_oe )
);
 
/////////////////////////////////////////////////////////////////////////////////////
// The SRAM controller
sram_top sram (
	.clk( wb_clk_i ),
	.rstn( resetn ),
	.wb_dat_i( wb_sr_dat_i ),
	.wb_dat_o( wb_sr_dat_o ),
	.wb_adr_i( wb_sr_adr_i ),
	.wb_sel_i( wb_sr_sel_i ),
	.wb_we_i(  wb_sr_we_i  ),
	.wb_cyc_i( wb_sr_cyc_i ),
	.wb_stb_i( wb_sr_stb_i ),
	.wb_ack_o( wb_sr_ack_o ),
	.wb_err_o( wb_sr_err_o ),
	.r_cen( sram_r_cen ),
	.r0_wen( sram_r0_wen ),
	.r1_wen( sram_r1_wen ),
	.r_oen( sram_r_oen ),
	.r_a( sram_r_a ),
	.r_d( sram_r_d ),
	.l_cen( sram_l_cen ),
	.l0_wen( sram_l0_wen ),
	.l1_wen( sram_l1_wen ),
	.l_oen( sram_l_oen ),
	.l_a( sram_l_a ),
	.l_d( sram_l_d )
);
 
/////////////////////////////////////////////////////////////////////////////////////
// The Traffic COP
//
tcop_top tcop (
	.clk( wb_clk_i ),
	.rstn( resetn ),
 
// The VGA connections
	.wb_vs_adr_i( wb_vs_adr_i ),
	.wb_vs_dat_i( wb_vs_dat_i ),
	.wb_vs_dat_o( wb_vs_dat_o ),
	.wb_vs_sel_i( wb_vs_sel_i ),
	.wb_vs_we_i(  wb_vs_we_i  ),
	.wb_vs_stb_i( wb_vs_stb_i ),
	.wb_vs_cyc_i( wb_vs_cyc_i ),
	.wb_vs_ack_o( wb_vs_ack_o ),
	.wb_vs_err_o( wb_vs_err_o ),
 
	.wb_vm_adr_o( wb_vm_adr_o ),
	.wb_vm_dat_i( wb_vm_dat_i ),
	.wb_vm_sel_o( wb_vm_sel_o ),
	.wb_vm_we_o(  wb_vm_we_o  ),
	.wb_vm_stb_o( wb_vm_stb_o ),
	.wb_vm_cyc_o( wb_vm_cyc_o ),
	.wb_vm_cab_o( wb_vm_cab_o ),
	.wb_vm_ack_i( wb_vm_ack_i ),
	.wb_vm_err_i( wb_vm_err_i ),
 
// The Development I/F
 
	.wb_dm_adr_o( wb_dm_adr_o ),
	.wb_dm_dat_i( wb_dm_dat_i ),
	.wb_dm_dat_o( wb_dm_dat_o ),
	.wb_dm_sel_o( wb_dm_sel_o ),
	.wb_dm_we_o(  wb_dm_we_o  ),
	.wb_dm_stb_o( wb_dm_stb_o ),
	.wb_dm_cyc_o( wb_dm_cyc_o ),
	.wb_dm_cab_o( wb_dm_cab_o ),
	.wb_dm_ack_i( wb_dm_ack_i ),
	.wb_dm_err_i( wb_dm_err_i ),
 
// The RISC connections 
 
	.wb_ri_cyc_o( wb_ri_cyc_o ),
	.wb_ri_adr_o( wb_ri_adr_o ),
	.wb_ri_dat_i( wb_ri_dat_i ),
	.wb_ri_dat_o( wb_ri_dat_o ),
	.wb_ri_sel_o( wb_ri_sel_o ),
	.wb_ri_ack_i( wb_ri_ack_i ),
	.wb_ri_err_i( wb_ri_err_i ),
	.wb_ri_rty_i( wb_ri_rty_i ),
	.wb_ri_we_o(  wb_ri_we_o  ),
	.wb_ri_stb_o( wb_ri_stb_o ),
 
	.wb_rd_cyc_o( wb_rd_cyc_o ),
	.wb_rd_adr_o( wb_rd_adr_o ),
	.wb_rd_dat_i( wb_rd_dat_i ),
	.wb_rd_dat_o( wb_rd_dat_o ),
	.wb_rd_sel_o( wb_rd_sel_o ),
	.wb_rd_ack_i( wb_rd_ack_i ),
	.wb_rd_err_i( wb_rd_err_i ),
	.wb_rd_rty_i( wb_rd_rty_i ),
	.wb_rd_we_o(  wb_rd_we_o  ),
	.wb_rd_stb_o( wb_rd_stb_o ),
 
// The SRAM
 
	.wb_sr_dat_i( wb_sr_dat_i ),
	.wb_sr_dat_o( wb_sr_dat_o ),
	.wb_sr_adr_i( wb_sr_adr_i ),
	.wb_sr_sel_i( wb_sr_sel_i ),
	.wb_sr_we_i(  wb_sr_we_i  ),
	.wb_sr_cyc_i( wb_sr_cyc_i ),
	.wb_sr_stb_i( wb_sr_stb_i ),
	.wb_sr_ack_o( wb_sr_ack_o ),
	.wb_sr_err_o( wb_sr_err_o ),
 
// The Flash RAM connections
 
	.wb_fl_dat_i( wb_fl_dat_i ),
	.wb_fl_dat_o( wb_fl_dat_o ),
	.wb_fl_adr_i( wb_fl_adr_i ),
	.wb_fl_sel_i( wb_fl_sel_i ),
	.wb_fl_we_i(  wb_fl_we_i  ),
	.wb_fl_cyc_i( wb_fl_cyc_i ),
	.wb_fl_stb_i( wb_fl_stb_i ),
	.wb_fl_ack_o( wb_fl_ack_o ),
	.wb_fl_err_o( wb_fl_err_o ),
 
// The Audio connections
 
	.wb_au_dat_i( wb_au_dat_i ),
	.wb_au_dat_o( wb_au_dat_o ),
	.wb_au_adr_i( wb_au_adr_i ),
	.wb_au_sel_i( wb_au_sel_i ),
	.wb_au_we_i(  wb_au_we_i  ),
	.wb_au_cyc_i( wb_au_cyc_i ),
	.wb_au_stb_i( wb_au_stb_i ),
	.wb_au_ack_o( wb_au_ack_o ),
	.wb_au_err_o( wb_au_err_o )
);
 
 
// Connecting all the leftovers
// synplicity 
 
always @(posedge wb_clk_i)
//	my_int <= $random;
	my_int <= 1'b0;
endmodule