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[/] [or1k/] [trunk/] [or1ksim/] [cpu/] [or1k/] [sprs.h] - Rev 167
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/* sprs.h -- OR1K architecture specific special-purpose registers Copyright (C) 1999 Damjan Lampret, lampret@opencores.org This file is part of OpenRISC 1000 Architectural Simulator. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include "spr_defs.h" typedef unsigned long sprword; /* Prototypes */ inline void mtspr(const int regno, const sprword value); inline sprword mfspr_(const int regno); #ifdef DEBUGMOD_OFF extern sprword sprs[MAX_SPRS]; extern int cont_run; /* defined in toplevel.c */ #define mfspr(regno)\ ((regno == SPR_SR && temp_disable_except > 0)?(sprs[regno] & ~SPR_SR_EXR)\ :((regno < MAX_SPRS)?(sprs[regno])\ :((printf("\nABORT: read out of SPR range %08X\n", regno),\ cont_run = 0)))) #else /* DEBUGMOD_OFF */ #define mfspr(regno) mfspr_(regno) #endif /* DEBUGMOD_OFF */ inline void setsprbit(const int regno, const int bitnum, const unsigned long bitvalue); inline int getsprbit(const int regno, const int bitnum); void sprs_status(); /* MM: If set, disables exceptions for temp_disable_except cycles. */ extern int temp_disable_except;
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