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/* 16450.c -- Simulation of 8250/16450 serial UART
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
/* This is functional simulation of 8250/16450 UARTs. Since we RX/TX data
   via file streams, we can't simulate modem control lines coming from the
   DCE and similar details of communication with the DCE.
 
   This simulated UART device is intended for basic UART device driver
   verification. From device driver perspective this device looks like a
   regular UART but never reports and modem control lines changes (the
   only DCE responses are incoming characters from the file stream).
*/
 
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
 
#include "config.h"
 
#ifdef HAVE_INTTYPES_H
#include <inttypes.h>
#endif
 
#include "port.h"
#include "arch.h"
#include "abstract.h"
#include "16450.h"
#include "sim-config.h"
#include "pic.h"
#include "vapi.h"
#include "sched.h"
#include "channel.h"
#include "debug.h"
 
DEFAULT_DEBUG_CHANNEL(uart);
 
#define MIN(a,b) ((a) < (b) ? (a) : (b))
 
void uart_tx_send(void *dat);
 
/* Number of clock cycles (one clock cycle is one call to the uart_clock())
   before a single character is transmitted or received. */
static unsigned long char_clks(int dll, int dlh, int lcr)
{
  unsigned int bauds_per_char = 2;
  unsigned long char_clks = ((dlh << 8) + dll);
 
  if (lcr & UART_LCR_PARITY)
    bauds_per_char += 2;
 
  /* stop bits 1 or two */
  if (lcr & UART_LCR_STOP)
    bauds_per_char += 4;
  else
    if ((lcr & 0x3) != 0)
      bauds_per_char += 2;
    else 
      bauds_per_char += 3;
 
  bauds_per_char += 10 + ((lcr & 0x3) << 1);
 
  return (char_clks * bauds_per_char) >> 1;
}
 
/*----------------------------------------------------[ Transmitter logic ]---*/
/* Sends the data in the shift register to the outside world */
static void send_char (struct dev_16450 *uart, int bits_send)
{
  PRINTF ("%c", (char)uart->iregs.txser);
  TRACE("TX \'%c\' via UART at %"PRIxADDR"\n", (char)uart->iregs.txser,
        uart->baseaddr);
  if (uart->regs.mcr & UART_MCR_LOOP)
    uart->iregs.loopback = uart->iregs.txser;
  else {
    /* Send to either VAPI or to file */
    if (uart->vapi_id) {
      int par, pe, fe, nbits;
      int j, data;
      unsigned long packet = 0;
 
      nbits = MIN (bits_send, (uart->regs.lcr & UART_LCR_WLEN8) + 5);
      /* Encode a packet */
      packet = uart->iregs.txser & ((1 << nbits) - 1);
 
      /* Calculate parity */
      for (j = 0, par = 0; j < nbits; j++)
        par ^= (packet >> j) & 1;
 
      if (uart->regs.lcr & UART_LCR_PARITY) {
        if (uart->regs.lcr & UART_LCR_SPAR) {
          packet |= 1 << nbits;
        } else {
          if (uart->regs.lcr & UART_LCR_EPAR)
            packet |= par << nbits;
          else
            packet |= (par ^ 1) << nbits;
        }
        nbits++;
      }
      packet |= 1 << (nbits++);
      if (uart->regs.lcr & UART_LCR_STOP)
        packet |= 1 << (nbits++);
 
      /* Decode a packet */
      nbits = (uart->vapi.lcr & UART_LCR_WLEN8) + 5;
      data = packet & ((1 << nbits) - 1);
 
      /* Calculate parity, including parity bit */
      for (j = 0, par = 0; j < nbits + 1; j++)
        par ^= (packet >> j) & 1;
 
      if (uart->vapi.lcr & UART_LCR_PARITY) {
        if (uart->vapi.lcr & UART_LCR_SPAR) {
          pe = !((packet >> nbits) & 1);
        } else {
          if (uart->vapi.lcr & UART_LCR_EPAR)
            pe = par != 0;
          else
            pe = par != 1;
        }
        nbits++;
      } else
        pe = 0;
 
      fe = ((packet >> (nbits++)) & 1) ^ 1;
      if (uart->vapi.lcr & UART_LCR_STOP)
        fe |= ((packet >> (nbits++)) & 1) ^ 1;
 
      TRACE ("lcr vapi %02x, uart %02x\n", uart->vapi.lcr, uart->regs.lcr);
      data |= (uart->vapi.lcr << 8) | (pe << 16) | (fe << 17) | (uart->vapi.lcr << 8);
      TRACE ("vapi_send (%08lx, %08x)\n", uart->vapi_id, data);
      vapi_send (uart->vapi_id, data);
    } else {
      char buffer[1] = { uart->iregs.txser & 0xFF };
      channel_write(uart->channel, buffer, 1);
    }
  }
}
 
/* Called when all the bits have been shifted out of the shift register */
void uart_char_clock(void *dat)
{
  struct dev_16450 *uart = dat;
 
  TRACE("Sending data in shift reg: 0x%02lx\n", uart->iregs.txser);
  /* We've sent all bits */
  send_char(uart, (uart->regs.lcr & UART_LCR_WLEN8) + 5); 
 
  if(!uart->istat.txbuf_full)
    uart->regs.lsr |= UART_LSR_TXSERE;
  else
    uart_tx_send(uart);
}
 
/* Called when a break has been shifted out of the shift register */
void uart_send_break(void *dat)
{
  struct dev_16450 *uart = dat;
 
  TRACE("Sending break\n");
#if 0
  /* Send broken frame */
  int nbits_sent = ((uart->regs.lcr & UART_LCR_WLEN8) + 5) * (uart->istat.txser_clks - 1) / uart->char_clks;
  send_char(i, nbits_sent);
#endif
  /* Send one break signal */
  vapi_send (uart->vapi_id, UART_LCR_SBC << 8);
 
  /* Send the next char (if there is one) */
  if(!uart->istat.txbuf_full)
    uart->regs.lsr |= UART_LSR_TXSERE;
  else
    uart_tx_send(uart);
}
 
/* Scheduled whenever the TX buffer has characters in it and we aren't sending
 * a character. */
void uart_tx_send(void *dat)
{
  struct dev_16450 *uart = dat;
 
  uart->iregs.txser = uart->regs.txbuf[uart->istat.txbuf_tail];
  uart->istat.txbuf_tail = (uart->istat.txbuf_tail + 1) % uart->fifo_len;
  uart->istat.txbuf_full--;
  uart->regs.lsr &= ~UART_LSR_TXSERE;
 
  TRACE("Moveing head of TX fifo (fill: %i) to shift reg 0x%02lx\n", 
        uart->istat.txbuf_full, uart->iregs.txser);
 
  /* Schedules a char_clock to run in the correct amount of time */
  if(!(uart->regs.lcr & UART_LCR_SBC)) {
    SCHED_ADD(uart_char_clock, uart, uart->char_clks * UART_CLOCK_DIVIDER);
  } else {
    TRACE("Sending break not char\n");
    SCHED_ADD(uart_send_break, uart, 0);
  }
 
  /* When UART is in either character mode, i.e. 16450 emulation mode, or FIFO
   * mode, the THRE interrupt is raised when THR transitions from full to empty.
   */
  if (!uart->istat.txbuf_full) {
    uart->regs.lsr |= UART_LSR_TXBUFE;
    uart->istat.thre_int = 1;
  }
}
 
/* Set a specific UART register with value. */
void uart_write_byte(oraddr_t addr, uint8_t value, void *dat)
{
  struct dev_16450 *uart = dat;
 
  TRACE("uart_write_byte(%"PRIxADDR",%02"PRIx8")\n", addr, value);
 
  if (uart->regs.lcr & UART_LCR_DLAB) {
    switch (addr) {
      case UART_DLL:
        uart->regs.dll = value;
        uart->char_clks = char_clks(uart->regs.dll, uart->regs.dlh, uart->regs.lcr);
        TRACE("\tSetting char_clks to %li (%02x, %02x, %02x)\n", uart->char_clks,
              uart->regs.dll, uart->regs.dlh, uart->regs.lcr);
        return;
      case UART_DLH:
        uart->regs.dlh = value;
        return;
    }
  }
 
  switch (addr) {
    case UART_TXBUF:
      uart->regs.lsr &= ~UART_LSR_TXBUFE;
      if (uart->istat.txbuf_full < uart->fifo_len) {
        uart->regs.txbuf[uart->istat.txbuf_head] = value;
        uart->istat.txbuf_head = (uart->istat.txbuf_head + 1) % uart->fifo_len;
        if(!uart->istat.txbuf_full++ && (uart->regs.lsr & UART_LSR_TXSERE))
          SCHED_ADD(uart_tx_send, uart, 0);
      } else
        uart->regs.txbuf[uart->istat.txbuf_head] = value;
 
      if (uart->regs.iir & UART_IIR_THRI)
	uart->istat.thre_int = 0;
      break;
    case UART_FCR:
      uart->regs.fcr = value & UART_VALID_FCR;
      if ((uart->fifo_len == 1 && (value & UART_FCR_FIE))
       || (uart->fifo_len != 1 && !(value & UART_FCR_FIE)))
        value |= UART_FCR_RRXFI | UART_FCR_RTXFI;
      uart->fifo_len = (value & UART_FCR_FIE) ? 16 : 1;
      if (value & UART_FCR_RTXFI) {
        uart->istat.txbuf_head = uart->istat.txbuf_tail = 0;
        uart->istat.txbuf_full = 0;
        uart->regs.lsr |= UART_LSR_TXBUFE;
 
	// For FIFO-mode only, THRE interrupt is set when THR and FIFO are empty
	uart->istat.thre_int = (uart->fifo_len == 16);
 
        SCHED_FIND_REMOVE(uart_tx_send, uart);
      }
      if (value & UART_FCR_RRXFI) {
        uart->istat.rxbuf_head = uart->istat.rxbuf_tail = 0;
        uart->istat.rxbuf_full = 0;
        uart->regs.lsr &= ~UART_LSR_RDRDY;
      }
      break;
    case UART_IER:
      uart->regs.ier = value & UART_VALID_IER;
      break;
    case UART_LCR:
      if((uart->regs.lcr & UART_LCR_SBC) != (value & UART_LCR_SBC)) {
        if((value & UART_LCR_SBC) && !(uart->regs.lsr & UART_LSR_TXSERE)) {
          /* Schedule a job to send the break char */
          SCHED_FIND_REMOVE(uart_char_clock, uart);
          SCHED_ADD(uart_send_break, uart, 0);
        }
        if(!(value & UART_LCR_SBC) && !(uart->regs.lsr & UART_LSR_TXSERE)) {
          /* Schedule a job to start sending characters */
          SCHED_ADD(uart_tx_send, uart, 0);
          /* Remove the uart_send_break job just in case it has not run yet */
          SCHED_FIND_REMOVE(uart_char_clock, uart);
        }
      }
      uart->regs.lcr = value & UART_VALID_LCR;
      uart->char_clks = char_clks(uart->regs.dll, uart->regs.dlh, uart->regs.lcr);
      break;
    case UART_MCR:
      uart->regs.mcr = value & UART_VALID_MCR;
      break;
    case UART_SCR:
      uart->regs.scr = value;
      break;
    default:
      TRACE("write out of range (addr %x)\n", addr);
  }
}
 
/* Read a specific UART register. */
uint8_t uart_read_byte(oraddr_t addr, void *dat)
{
  struct dev_16450 *uart = dat;
  uint8_t value = 0;
 
  TRACE("uart_read_byte(%"PRIxADDR")", addr);
 
  if (uart->regs.lcr & UART_LCR_DLAB) {
    switch (addr) {
      case UART_DLL:
        value = uart->regs.dll;
        TRACE("= %"PRIx8"\n", value);
        return value;
      case UART_DLH:
        value = uart->regs.dlh;
        TRACE("= %"PRIx8"\n", value);
        return value;
    }
  }
 
  switch (addr) {
    case UART_RXBUF:
      { /* Print out FIFO for debugging */
        int i;
        TRACE("(%i/%i, %i, %i:", uart->istat.rxbuf_full, uart->fifo_len,
              uart->istat.rxbuf_head, uart->istat.rxbuf_tail);
        for (i = 0; i < uart->istat.rxbuf_full; i++)
          TRACE("%02x ", uart->regs.rxbuf[(uart->istat.rxbuf_tail + i) % uart->fifo_len]);
        TRACE(")");
      }
      if (uart->istat.rxbuf_full) {
        value = uart->regs.rxbuf[uart->istat.rxbuf_tail];
        uart->istat.rxbuf_tail = (uart->istat.rxbuf_tail + 1) % uart->fifo_len;
        uart->istat.rxbuf_full--;
      }
 
      if (uart->istat.rxbuf_full)
        uart->regs.lsr |= UART_LSR_RDRDY;
      else
        uart->regs.lsr &= ~UART_LSR_RDRDY;
 
      uart->istat.timeout_count = 0;
      break;
    case UART_IER:
      value = uart->regs.ier & UART_VALID_IER;
      break;
    case UART_IIR:
      value = (uart->regs.iir & UART_VALID_IIR) | 0xc0;
      if (uart->regs.iir & UART_IIR_THRI)
        uart->istat.thre_int = 0;
      break;
    case UART_LCR:
      value = uart->regs.lcr & UART_VALID_LCR;
      break;
    case UART_MCR:
      value = 0;
      break;
    case UART_LSR:
      value = uart->regs.lsr & UART_VALID_LSR;
      uart->regs.lsr &=
        ~(UART_LSR_OVRRUN | UART_LSR_BREAK | UART_LSR_PARITY
         | UART_LSR_FRAME | UART_LSR_RXERR);
      break;
    case UART_MSR:
      value = uart->regs.msr & UART_VALID_MSR;
      uart->regs.msr = 0;
      break;
    case UART_SCR:
      value = uart->regs.scr;
      break;
    default:
      TRACE("read out of range (addr %"PRIxADDR")\n", addr);
  }
  TRACE(" = %"PRIx8"\n", value);
  return value;
}
 
/*--------------------------------------------------------[ VAPI handling ]---*/
/* Decodes the read vapi command */
static void uart_vapi_cmd(struct dev_16450 *uart)
{
  int received = 0;
 
  while (!received) {
    if (uart->vapi_buf_head_ptr != uart->vapi_buf_tail_ptr) {
      unsigned long data = uart->vapi_buf[uart->vapi_buf_tail_ptr];
      TRACE("\tHandling: %08lx (%i,%i)\n", data, uart->vapi_buf_head_ptr,
            uart->vapi_buf_tail_ptr);
      uart->vapi_buf_tail_ptr = (uart->vapi_buf_tail_ptr + 1) % UART_VAPI_BUF_LEN;
      switch (data >> 24) {
      case 0x00:
        uart->vapi.lcr = (data >> 8) & 0xff;
        /* Put data into rx fifo */
        uart->iregs.rxser = data & 0xff;
        uart->vapi.char_clks = char_clks (uart->vapi.dll, uart->vapi.dlh, uart->vapi.lcr);
        if((uart->vapi.lcr & ~UART_LCR_SBC) != (uart->regs.lcr & ~UART_LCR_SBC)
            || uart->vapi.char_clks != uart->char_clks
            || uart->vapi.skew < -MAX_SKEW || uart->vapi.skew > MAX_SKEW) {
          if((uart->vapi.lcr & ~UART_LCR_SBC) != (uart->regs.lcr & ~UART_LCR_SBC))
            WARN("unmatched VAPI (%02"PRIx8") and uart (%02"PRIx8") modes.\n",
                 uart->vapi.lcr & ~UART_LCR_SBC, uart->regs.lcr & ~UART_LCR_SBC);
          if(uart->vapi.char_clks != uart->char_clks) {
            WARN("unmatched VAPI (%li) and uart (%li) char clocks.\n",
                 uart->vapi.char_clks, uart->char_clks);
            WARN("VAPI: lcr: %02"PRIx8", dll: %02"PRIx8", dlh: %02"PRIx8"\n",
                 uart->vapi.lcr, uart->vapi.dll, uart->vapi.dlh);
            WARN("UART: lcr: %02"PRIx8", dll: %02"PRIx8", dlh: %02"PRIx8"\n",
                 uart->regs.lcr, uart->regs.dll, uart->vapi.dlh);
          }
          if(uart->vapi.skew < -MAX_SKEW || uart->vapi.skew > MAX_SKEW)
            WARN("VAPI skew is beyond max: %i\n", uart->vapi.skew);
          /* Set error bits */
          uart->iregs.rxser |= (UART_LSR_FRAME | UART_LSR_RXERR) << 8;
          if(uart->regs.lcr & UART_LCR_PARITY)
            uart->iregs.rxser |= UART_LSR_PARITY << 8;
        }
        uart->istat.rxser_full = 1;
        received = 1;
        break;
      case 0x01:
        uart->vapi.dll = (data >> 0) & 0xff;
        uart->vapi.dlh = (data >> 8) & 0xff;
        break;
      case 0x02:
        uart->vapi.lcr = (data >> 8) & 0xff;
        break;
      case 0x03:
        uart->vapi.skew = (signed short)(data & 0xffff);
        break;
      case 0x04:
        uart->vapi.next_break_cnt = data & 0xffff;
        uart->vapi.next_break = (data >> 16) & 1;
        break;
      default:
        WARN("WARNING: Invalid vapi command %02lx\n", data >> 24);
        break;
      }
    } else break;
  }
}
 
/* Function that handles incoming VAPI data.  */
void uart_vapi_read (unsigned long id, unsigned long data, void *dat)
{
  struct dev_16450 *uart = dat;
  TRACE("UART: id %08lx, data %08lx\n", id, data);
  uart->vapi_buf[uart->vapi_buf_head_ptr] = data;
  uart->vapi_buf_head_ptr = (uart->vapi_buf_head_ptr + 1) % UART_VAPI_BUF_LEN;
  if (uart->vapi_buf_tail_ptr == uart->vapi_buf_head_ptr) {
    fprintf (stderr, "FATAL: uart VAPI buffer to small.\n");
    exit (1);
  }
}
 
/* Adds a character to the FIFO */
 
void uart_add_char (struct dev_16450 *uart, int ch)
{
  if (uart->istat.rxbuf_full + 1 > uart->fifo_len)
    uart->regs.lsr |= UART_LSR_OVRRUN | UART_LSR_RXERR;
  else {
    TRACE("add %02x\n", ch);
    uart->regs.rxbuf[uart->istat.rxbuf_head] = ch;
    uart->istat.rxbuf_head = (uart->istat.rxbuf_head + 1) % uart->fifo_len;
    uart->istat.rxbuf_full++;
  }
  uart->regs.lsr |= UART_LSR_RDRDY;
  uart->istat.timeout_count = 0;
}
 
/* Simulation hook. Must be called every clock cycle to simulate all UART
   devices. It does internal functional UART simulation. */
void uart_clock16 (void *dat)
{
  struct dev_16450 *uart = dat;
  int retval;
 
  /* Schedule for later */
  SCHED_ADD (uart_clock16, dat, UART_CLOCK_DIVIDER);
 
  TRACE("Running uart clock:\n");
 
  /* If VAPI is not selected, UART communicates with two file streams;
     if VAPI is selected, we use VAPI streams.  */
  /* if txfs is corrupted, skip this uart. */
  if (!uart->vapi_id && !channel_ok(uart->channel)) return;
 
  TRACE("\tChannel stream or VAPI checks out ok\n");
 
  if (uart->vapi.next_break_cnt >= 0)
    if (--uart->vapi.next_break_cnt < 0) {
      if (!(uart->vapi.cur_break = uart->vapi.next_break))
        uart->istat.break_set = 0;
    }
 
  /***************** Receive *****************/
 
  /* Is there a break? */
  if (uart->vapi.cur_break) {
    uart->vapi.cur_break_cnt++;
    if (uart->vapi.cur_break_cnt > UART_BREAK_COUNT * uart->vapi.char_clks) {
      if (!uart->istat.break_set) {
        unsigned lsr;
        uart->istat.break_set = 1;
        lsr = UART_LSR_BREAK | UART_LSR_RXERR | UART_LSR_RDRDY;
        PRINTF ("[%x]\n", uart->regs.lsr);
        uart->istat.rxser_full = 0;
        uart->istat.rxser_clks = 0;
        uart_add_char (uart, lsr << 8);
      } else
        uart->vapi.cur_break_cnt = 0;
    }
    if (uart->istat.rxser_full) {
      uart->istat.rxser_full = 0;
      uart->istat.rxser_clks = 0;
    }
  } else {
    if (uart->istat.rxser_full) {
      if (uart->char_clks <= uart->istat.rxser_clks++) {
        /* Set unused character bits to zero and allow lsr register in fifo */
        uart->iregs.rxser &= ((1 << ((uart->regs.lcr & 3) + 5)) - 1) | 0xff00;
        TRACE("\tReceiving 0x%02lx'%c' via UART (at %"PRIxADDR"...\n",
              uart->iregs.rxser, (char)uart->iregs.rxser, uart->baseaddr);
	PRINTF ("%c", (char)uart->iregs.rxser);
        uart->istat.rxser_full = 0;
        uart->istat.rxser_clks = 0;
        uart_add_char (uart, uart->iregs.rxser);
      }
    }
  }
 
  /* Check if there is something waiting, and put it into rxser */
  if (uart->regs.mcr & UART_MCR_LOOP) {
    uart->iregs.rxser = uart->iregs.loopback;
    uart->istat.rxser_full = 1;
  } else {
    if (!uart->vapi_id) {
      if(uart->istat.rxser_full == 0) {
        if (uart->slowdown)
          uart->slowdown--;
        else {
	  char buffer[1];
	  retval = channel_read(uart->channel, buffer, 1);
	  if(retval < 0)
		  perror(uart->channel_str);
	  else if(retval > 0) {
            uart->iregs.rxser = (unsigned char)buffer[0];
            uart->istat.rxser_full = 1;
	  } else
            uart->slowdown = UART_FGETC_SLOWDOWN;
	}
      }
    } else { /* VAPI */
      /* do not handle commands while receiving */
      if (uart->istat.rxser_full) return;
      uart_vapi_cmd(uart);
    }
  }
 
  /***************** Loopback *****************/
  if (uart->regs.mcr & UART_MCR_LOOP) {
    TRACE("uart_clock: Loopback\n");
    if ((uart->regs.mcr & UART_MCR_AUX2) !=
        ((uart->regs.msr & UART_MSR_DCD) >> 4))
      uart->regs.msr |= UART_MSR_DDCD;
    if ((uart->regs.mcr & UART_MCR_AUX1) <
        ((uart->regs.msr & UART_MSR_RI) >> 4))
      uart->regs.msr |= UART_MSR_TERI;
    if ((uart->regs.mcr & UART_MCR_RTS) !=
        ((uart->regs.msr & UART_MSR_CTS) >> 3))
      uart->regs.msr |= UART_MSR_DCTS;
    if ((uart->regs.mcr & UART_MCR_DTR) !=
        ((uart->regs.msr & UART_MSR_DSR) >> 5))
      uart->regs.msr |= UART_MSR_DDSR;
    uart->regs.msr &= ~(UART_MSR_DCD | UART_MSR_RI
              | UART_MSR_DSR | UART_MSR_CTS);
    uart->regs.msr |= ((uart->regs.mcr & UART_MCR_AUX2) << 4);
    uart->regs.msr |= ((uart->regs.mcr & UART_MCR_AUX1) << 4);
    uart->regs.msr |= ((uart->regs.mcr & UART_MCR_RTS) << 3);
    uart->regs.msr |= ((uart->regs.mcr & UART_MCR_DTR) << 5);
  }
 
  if (uart->regs.lsr & UART_LSR_RDRDY)
    uart->istat.timeout_count++;
 
  /* Update LSR error bits from the ones from rx FIFO */
  if (uart->istat.rxbuf_full) {
    uart->regs.lsr |= uart->regs.rxbuf[uart->istat.rxbuf_tail] >> 8;
    /* we must delete the lsr status, so that we can clear it from lsr */
    uart->regs.rxbuf[uart->istat.rxbuf_tail] &= 0xff;
  }
 
  /* Interrupt detection in proper priority order. */
  uart->regs.iir = UART_IIR_NO_INT;
  if (uart->regs.ier & UART_IER_RLSI &&                    /* Receiver LS */
      uart->regs.lsr & (UART_LSR_OVRRUN | UART_LSR_PARITY
        | UART_LSR_FRAME | UART_LSR_BREAK)) {
    uart->regs.iir = UART_IIR_RLSI;
  } else if ((uart->regs.ier & UART_IER_RDI)               /* RD available */
      && (uart->istat.rxbuf_full >= UART_FIFO_TRIGGER(uart->regs.fcr >> 6))
      && (uart->regs.lsr & UART_LSR_RDRDY)) {
    uart->regs.iir = UART_IIR_RDI;
  } else if ((uart->regs.ier & UART_IER_RDI)               /* timeout */
      && (uart->istat.timeout_count >= UART_CHAR_TIMEOUT * uart->char_clks)
      && (uart->istat.rxbuf_head != uart->istat.rxbuf_tail)) {
    uart->regs.iir = UART_IIR_CTI;
  } else if (uart->regs.ier & UART_IER_THRI &&             /* Transm. empty */
      uart->istat.thre_int == 1) {
    uart->regs.iir = UART_IIR_THRI;
  } else if (uart->regs.ier & UART_IER_MSI &&              /* Modem status */
      uart->regs.msr & (UART_MSR_DCTS | UART_MSR_DDSR
        | UART_MSR_TERI | UART_MSR_DDCD)) {
    uart->regs.iir = UART_IIR_MSI;
  }
  if (!(uart->regs.iir & UART_IIR_NO_INT)) {
    TRACE("\tuart->regs.iir = %i\t", uart->regs.iir);
    report_interrupt(uart->irq);
  }
}
 
/* Reset.  It initializes all registers of all UART devices to zero values,
   (re)opens all RX/TX file streams and places devices in memory address
   space.  */
void uart_reset(void *dat)
{
  struct dev_16450 *uart = dat;
 
  if(uart->vapi_id) {
    vapi_install_handler(uart->vapi_id, uart_vapi_read, dat);
  } else if (uart->channel_str && uart->channel_str[0]) { /* Try to create stream. */
    if(uart->channel)
      channel_close(uart->channel);
    else
      uart->channel = channel_init(uart->channel_str);
    if(channel_open(uart->channel) < 0) {
      WARN ("WARNING: problem with channel \"%s\" detected.\n", uart->channel_str);
    } else if (config.sim.verbose)
      PRINTF("UART at 0x%"PRIxADDR"\n", uart->baseaddr);
  } else {
    WARN ("WARNING: UART at %"PRIxADDR" has no vapi nor channel specified\n",
          uart->baseaddr);
  }
 
  if (uart->uart16550)
    uart->fifo_len = 16;
  else
    uart->fifo_len = 1;
 
  uart->istat.rxbuf_head = uart->istat.rxbuf_tail = 0;
  uart->istat.txbuf_head = uart->istat.txbuf_tail = 0;
 
  uart->istat.rxser_full = 0;
  uart->istat.txbuf_full = uart->istat.rxbuf_full = 0;
 
  uart->istat.rxser_clks = 0;
 
  uart->istat.thre_int = 0;
  uart->istat.break_set = 0;
  uart->istat.timeout_count = 0;
 
  // For FIFO-mode only, THRE interrupt is set when both THR and FIFO are empty
  uart->istat.thre_int = (uart->fifo_len == 16);
 
  uart->char_clks = 0;
  uart->slowdown = UART_FGETC_SLOWDOWN;
 
  uart->iregs.txser = 0;
  uart->iregs.rxser = 0;
  uart->iregs.loopback = 0;
 
  memset(uart->regs.txbuf, 0, sizeof(uart->regs.txbuf));
  memset(uart->regs.rxbuf, 0, sizeof(uart->regs.rxbuf));
 
  uart->regs.dll = 0;
  uart->regs.dlh = 0;
  uart->regs.ier = 0;
  uart->regs.iir = 0;
  uart->regs.fcr = 0;
  uart->regs.lcr = UART_LCR_RESET;
  uart->regs.mcr = 0;
  uart->regs.lsr = UART_LSR_TXBUFE | UART_LSR_TXSERE;
  uart->regs.msr = 0;
  uart->regs.scr = 0;
 
  uart->vapi.cur_break = uart->vapi.cur_break_cnt = uart->vapi.next_break = 0;
  uart->vapi.next_break_cnt = -1;
  uart->vapi.skew = 0;
  uart->vapi.lcr = 0;
  uart->vapi.dll = 0;
  uart->vapi.char_clks = 0;
 
  uart->vapi_buf_head_ptr = 0;
  uart->vapi_buf_tail_ptr = 0;
  memset(uart->vapi_buf, 0, sizeof(uart->vapi_buf));
 
  SCHED_ADD (uart_clock16, dat, UART_CLOCK_DIVIDER);
}
 
/* Print register values on stdout. */
void uart_status(void *dat)
{
  struct dev_16450 *uart = dat;
  int i;
 
  PRINTF("\nUART visible registers at 0x%"PRIxADDR":\n", uart->baseaddr);
  PRINTF("RXBUF: ");
  for (i = uart->istat.rxbuf_head; i != uart->istat.rxbuf_tail; i = (i + 1) % uart->fifo_len)
    PRINTF (" %.2x", uart->regs.rxbuf[i]);
  PRINTF("TXBUF: ");
  for (i = uart->istat.txbuf_head; i != uart->istat.txbuf_tail; i = (i + 1) % uart->fifo_len)
    PRINTF (" %.2x", uart->regs.txbuf[i]);
  PRINTF("\n");
  PRINTF("DLL  : %.2x  DLH  : %.2x\n", uart->regs.dll, uart->regs.dlh);
  PRINTF("IER  : %.2x  IIR  : %.2x\n", uart->regs.ier, uart->regs.iir);
  PRINTF("LCR  : %.2x  MCR  : %.2x\n", uart->regs.lcr, uart->regs.mcr);
  PRINTF("LSR  : %.2x  MSR  : %.2x\n", uart->regs.lsr, uart->regs.msr);
  PRINTF("SCR  : %.2x\n", uart->regs.scr);
 
  PRINTF("\nInternal registers (sim debug):\n");
  PRINTF("RXSER: %.2lx  TXSER: %.2lx\n", uart->iregs.rxser, uart->iregs.txser);
 
  PRINTF("\nInternal status (sim debug):\n");
  PRINTF("char_clks: %ld\n", uart->char_clks);
  PRINTF("rxser_clks: %ld\n", uart->istat.rxser_clks);
  PRINTF("rxser: %d\n", uart->istat.rxser_full);
  PRINTF("rxbuf_full: %d  txbuf_full: %d\n", uart->istat.rxbuf_full, uart->istat.txbuf_full);
  PRINTF("Using IRQ%i\n", uart->irq);
  if (uart->vapi_id)
    PRINTF ("Connected to vapi ID=%lx\n\n", uart->vapi_id);
  /* TODO: replace by a channel_status
  else
    PRINTF("RX fs: %p  TX fs: %p\n\n", uart->rxfs, uart->txfs);
  */
}
 
/*---------------------------------------------------[ UART configuration ]---*/
void uart_baseaddr(union param_val val, void *dat)
{
  struct dev_16450 *uart = dat;
  uart->baseaddr = val.addr_val;
}
 
void uart_jitter(union param_val val, void *dat)
{
  struct dev_16450 *uart = dat;
  uart->jitter = val.int_val;
}
 
void uart_irq(union param_val val, void *dat)
{
  struct dev_16450 *uart = dat;
  uart->irq = val.int_val;
}
 
void uart_16550(union param_val val, void *dat)
{
  struct dev_16450 *uart = dat;
  uart->uart16550 = val.int_val;
}
 
void uart_channel(union param_val val, void *dat)
{
  struct dev_16450 *uart = dat;
  if(!(uart->channel_str = strdup(val.str_val))) {
    fprintf(stderr, "Peripheral 16450: Run out of memory\n");
    exit(-1);
  }
}
 
void uart_newway(union param_val val, void *dat)
{
  CONFIG_ERROR(" txfile and rxfile and now obsolete.\n\tUse 'channel = \"file:rxfile,txfile\"' instead.");
  exit(1);
}
 
void uart_vapi_id(union param_val val, void *dat)
{
  struct dev_16450 *uart = dat;
  uart->vapi_id = val.int_val;
}
 
void uart_enabled(union param_val val, void *dat)
{
  struct dev_16450 *uart = dat;
  uart->enabled = val.int_val;
}
 
void *uart_sec_start(void)
{
  struct dev_16450 *new = malloc(sizeof(struct dev_16450));
 
  if(!new) {
    fprintf(stderr, "Peripheral 16450: Run out of memory\n");
    exit(-1);
  }
 
  new->enabled = 1;
  new->channel_str = NULL;
  new->channel = NULL;
  new->vapi_id = 0;
 
  return new;
}
 
void uart_sec_end(void *dat)
{
  struct dev_16450 *uart = dat;
  struct mem_ops ops;
 
  if(!uart->enabled) {
    free(dat);
    return;
  }
 
  memset(&ops, 0, sizeof(struct mem_ops));
 
  ops.readfunc8 = uart_read_byte;
  ops.writefunc8 = uart_write_byte;
  ops.read_dat8 = dat;
  ops.write_dat8 = dat;
 
  /* FIXME: What should these be? */
  ops.delayr = 2;
  ops.delayw = 2;
 
  reg_mem_area(uart->baseaddr, UART_ADDR_SPACE, 0, &ops);
 
  reg_sim_reset(uart_reset, dat);
  reg_sim_stat(uart_status, dat);
}
 
void reg_uart_sec(void)
{
  struct config_section *sec = reg_config_sec("uart", uart_sec_start,
                                              uart_sec_end);
 
  reg_config_param(sec, "baseaddr", paramt_addr, uart_baseaddr);
  reg_config_param(sec, "enabled", paramt_int, uart_enabled);
  reg_config_param(sec, "irq", paramt_int, uart_irq);
  reg_config_param(sec, "16550", paramt_int, uart_16550);
  reg_config_param(sec, "jitter", paramt_int, uart_jitter);
  reg_config_param(sec, "channel", paramt_str, uart_channel);
  reg_config_param(sec, "txfile", paramt_str, uart_newway);
  reg_config_param(sec, "rxfile", paramt_str, uart_newway);
  reg_config_param(sec, "vapi_id", paramt_int, uart_vapi_id);
}