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[/] [or1k/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [ethernet.old/] [eth_fifo.v] - Rev 1765
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////////////////////////////////////////////////////////////////////// //// //// //// eth_fifo.v //// //// //// //// This file is part of the Ethernet IP core project //// //// http://www.opencores.org/projects/ethmac/ //// //// //// //// Author(s): //// //// - Igor Mohor (igorM@opencores.org) //// //// //// //// All additional information is avaliable in the Readme.txt //// //// file. //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2001 Authors //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // CVS Revision History // // $Log: not supported by cvs2svn $ // Revision 1.1 2002/02/05 16:44:39 mohor // Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 // MHz. Statuses, overrun, control frame transmission and reception still need // to be fixed. // // `include "timescale.v" module eth_fifo (data_in, data_out, clk, reset, write, read, clear, almost_full, full, almost_empty, empty); parameter DATA_WIDTH = 32; parameter DEPTH = 8; parameter CNT_WIDTH = 4; parameter Tp = 1; input clk; input reset; input write; input read; input clear; input [DATA_WIDTH-1:0] data_in; output [DATA_WIDTH-1:0] data_out; output almost_full; output full; output almost_empty; output empty; reg [DATA_WIDTH-1:0] fifo [0:DEPTH-1]; reg [CNT_WIDTH-1:0] cnt; reg [CNT_WIDTH-2:0] read_pointer; reg [CNT_WIDTH-2:0] write_pointer; always @ (posedge clk or posedge reset) begin if(reset) cnt <=#Tp 0; else if(clear) cnt <=#Tp 0; else if(read ^ write) if(read) cnt <=#Tp cnt - 1'b1; else cnt <=#Tp cnt + 1'b1; end always @ (posedge clk or posedge reset) begin if(reset) read_pointer <=#Tp 0; else if(clear) read_pointer <=#Tp 0; else if(read & ~empty) read_pointer <=#Tp read_pointer + 1'b1; end always @ (posedge clk or posedge reset) begin if(reset) write_pointer <=#Tp 0; else if(clear) write_pointer <=#Tp 0; else if(write & ~full) write_pointer <=#Tp write_pointer + 1'b1; end assign empty = ~(|cnt); assign almost_empty = cnt == 1; assign full = cnt == DEPTH; assign almost_full = &cnt[CNT_WIDTH-2:0]; always @ (posedge clk) begin if(write & ~full) fifo[write_pointer] <=#Tp data_in; end assign data_out = fifo[read_pointer]; endmodule