Subversion Repositories or1k

+libext+.v
+access+wr
+overwrite
+mess
+tcl+sim.tcl
+max_err_count+2
 
//
// Test bench files
//
+incdir+../../bench/verilog
../../bench/verilog/xess_top.v
//../../bench/verilog/or1200_monitor.v
// ../../bench/verilog/sram_init.v
// ../../bench/verilog/dbg_comm.v
../../bench/verilog/xcv_glbl.v
 
//
// Models
//
../../bench/models/512Kx8.v
../../bench/models/vga_model.v
../../bench/models/codec_model.v
+incdir+../../bench/models/28f016s3
../../bench/models/28f016s3/bwsvff.v
../../bench/verilog/dbg_if_model.v
../../bench/verilog/wb_master.v
 
//
// RTL files (top)
//
+incdir+../../rtl/verilog
../../rtl/verilog/xsv_fpga_top.v
../../rtl/verilog/tc_top.v
../../rtl/verilog/tdm_slave_if.v
 
//
// RTL files (audio)
//
+incdir+../../rtl/verilog/audio
../../rtl/verilog/audio/audio_codec_if.v
../../rtl/verilog/audio/audio_top.v
../../rtl/verilog/audio/audio_wb_if.v
../../rtl/verilog/audio/fifo_4095_16.v
../../rtl/verilog/audio/fifo_empty_16.v
 
//
// RTL files (mem_if)
//
+incdir+../../rtl/verilog/mem_if
../../rtl/verilog/mem_if/flash_top.v
../../rtl/verilog/mem_if/sram_top.v
 
//
// RTL files (dbg_interface)
//
+incdir+../../rtl/verilog/dbg_interface
../../rtl/verilog/dbg_interface/dbg_crc8_d1.v
../../rtl/verilog/dbg_interface/dbg_defines.v
../../rtl/verilog/dbg_interface/dbg_register.v
../../rtl/verilog/dbg_interface/dbg_registers.v
../../rtl/verilog/dbg_interface/dbg_sync_clk1_clk2.v
../../rtl/verilog/dbg_interface/dbg_top.v
../../rtl/verilog/dbg_interface/dbg_trace.v
 
//
// RTL files (ssvga)
//
+incdir+../../rtl/verilog/ssvga
../../rtl/verilog/ssvga/crtc_iob.v
../../rtl/verilog/ssvga/ssvga_crtc.v
../../rtl/verilog/ssvga/ssvga_defines.v
../../rtl/verilog/ssvga/ssvga_fifo.v
../../rtl/verilog/ssvga/ssvga_top.v
../../rtl/verilog/ssvga/ssvga_wbm_if.v
../../rtl/verilog/ssvga/ssvga_wbs_if.v
 
//
// RTL files (ethernet)
//
+incdir+../../rtl/verilog/ethernet
../../rtl/verilog/ethernet/eth_clockgen.v
../../rtl/verilog/ethernet/eth_crc.v
../../rtl/verilog/ethernet/eth_fifo.v
../../rtl/verilog/ethernet/eth_maccontrol.v
../../rtl/verilog/ethernet/eth_macstatus.v
../../rtl/verilog/ethernet/eth_miim.v
../../rtl/verilog/ethernet/eth_outputcontrol.v
../../rtl/verilog/ethernet/eth_random.v
../../rtl/verilog/ethernet/eth_receivecontrol.v
../../rtl/verilog/ethernet/eth_register.v
../../rtl/verilog/ethernet/eth_registers.v
../../rtl/verilog/ethernet/eth_rxaddrcheck.v
../../rtl/verilog/ethernet/eth_rxcounters.v
../../rtl/verilog/ethernet/eth_rxethmac.v
../../rtl/verilog/ethernet/eth_rxstatem.v
../../rtl/verilog/ethernet/eth_shiftreg.v
../../rtl/verilog/ethernet/eth_transmitcontrol.v
../../rtl/verilog/ethernet/eth_txcounters.v
../../rtl/verilog/ethernet/eth_txethmac.v
../../rtl/verilog/ethernet/eth_txstatem.v
../../rtl/verilog/ethernet/eth_wishbone.v
../../rtl/verilog/ethernet/eth_spram_256x32.v
../../rtl/verilog/ethernet/eth_top.v
 
//
// RTL files (uart16550)
//
+incdir+../../rtl/verilog/uart16550
../../rtl/verilog/uart16550/raminfr.v
../../rtl/verilog/uart16550/uart_debug_if.v
../../rtl/verilog/uart16550/uart_tfifo.v
../../rtl/verilog/uart16550/uart_rfifo.v
../../rtl/verilog/uart16550/uart_receiver.v
../../rtl/verilog/uart16550/uart_regs.v
../../rtl/verilog/uart16550/uart_transmitter.v
../../rtl/verilog/uart16550/uart_wb.v
../../rtl/verilog/uart16550/uart_top.v
 
//
// RTL files (ps2)
//
+incdir+../../rtl/verilog/ps2
../../rtl/verilog/ps2/ps2_io_ctrl.v
../../rtl/verilog/ps2/ps2_keyboard.v
../../rtl/verilog/ps2/ps2_translation_table.v
../../rtl/verilog/ps2/ps2_wb_if.v
../../rtl/verilog/ps2/ps2_top.v
 
//
// RTL files (or1200)
//
+incdir+../../rtl/verilog/or1200
../../rtl/verilog/or1200/or1200_wb_biu.v
../../../../or1200/syn/synopsys/out/xxx_or1200_topxx.v
 
//
// Library files
//
+incdir+../../syn
../../syn/vs_sc.v
../../syn/vs_hdsp_1024x32.v
../../syn/vs_hdsp_1024x8.v
../../syn/vs_hdsp_2048x32.v
../../syn/vs_hdsp_2048x8.v
../../syn/vs_hdsp_256x32.v
../../syn/vs_hdsp_512x20.v
../../syn/vs_hdsp_64x14.v
../../syn/vs_hdsp_64x22.v
../../syn/vs_hdsp_64x24.v
../../syn/vs_hdtp_32x32.v
+incdir+../../lib/xilinx/coregen
../../lib/xilinx/coregen/XilinxCoreLib/async_fifo_v3_0.v
+incdir+../../lib/xilinx/unisims
../../lib/xilinx/unisims/RAMB4_S16.v
../../lib/xilinx/unisims/RAMB4_S8.v
../../lib/xilinx/unisims/RAMB4_S4.v
../../lib/xilinx/unisims/RAMB4_S2.v
../../lib/xilinx/unisims/RAMB4_S16_S16.v
../../lib/xilinx/unisims/RAM32X1D.v
../../lib/xilinx/unisims/RAMB4_S8_S16.v
../../lib/xilinx/unisims/IBUFG.v
../../lib/xilinx/unisims/BUFG.v
../../lib/xilinx/unisims/CLKDLL.v