Subversion Repositories or1k

//////////////////////////////////////////////////////////////////////
////                                                              ////
////  ZBT RAM Model                                               ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Emulates the behaviour of the ZBT RAM                       ////
////                                                              ////
////  To Do:                                                      ////
////   - nothing really                                           ////
////                                                              ////
////  Author(s):                                                  ////
////      - Javier Castillo, javier.castillo@urjc.es              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 OpenCores                                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2004/12/13 17:14:31  jcastillo
// Firt import of OR1200 over Celoxica RC203 platform
//
 
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
 
module zbtram(clk,nBW,nCS,nRW,data,address);
 
   input        clk;
   input [3:0]  nBW;
   input        nCS;
   input        nRW;
   inout [31:0] data;
   input [19:0] address;
 
   reg   [19:0] addr_var;
   reg   [31:0] mem['h0:'h10000];
 
   reg control;
   reg [31:0] data_t;
 
   assign #1 data = control ? data_t : 32'hZ;
 
   integer i,file;
 
   initial
   begin
 
      #1
 
      for(i='h0;i<'h10000;i=i+1)
        mem[i]=0; 
 
      //Load RAM with a initial program
 /*   $display("Initializing RAM");
      $readmemh("./hex/or1k-des.hex", mem); */
 
 
 
      data_t=0;
      control=0;
 
      while(1)
      begin
          @(posedge clk)
          if(nRW==1)
          begin
            addr_var = address;
 
            control = 1;
            data_t = mem[addr_var]; 
            if(addr_var==0) data_t=0;
//          $display("Read %X from address %X",data_t,addr_var);   
          end
          else
          begin
            addr_var = address;
            control = 0;
            @(posedge clk)
            case(nBW)
             4'b0000:
               mem[addr_var] = data;
             4'b0111:             
               mem[addr_var][31:24] = data[7:0];
             4'b1011:             
               mem[addr_var][23:16] = data[7:0];
             4'b1101:             
               mem[addr_var][15:8] = data[7:0];
             4'b1110:             
               mem[addr_var][7:0] = data[7:0];
             4'b0011:             
               mem[addr_var][31:16] = data[15:0];
             4'b1100:             
               mem[addr_var][15:0] = data[15:0];
            endcase    
            control = 1;
//            $display("%d: Write %X in address %X sel= %b",$time,mem[addr_var],addr_var,nBW);   
          end
       end      
    end	  
 
 
 
endmodule