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Notes on running this design on an RC200:

Building the hardware
---------------------
* Synthesise using Synplicity and the script: syn/synplicity/rc200.tcl.

* Place-and-route the resulting edif (rc200soc.edf) along with
  the constraint file: backend/xilinx/rc200soc.ucf

* Note: I found that with ISE 7.1.04i, and Synplify Pro 8.0 I was unable meet
  the timing for a 50 MHz clock (as selected in the UCF). In practice though
  the error margin is narrow enough for the design to probably work anyway.


Building the software
---------------------
* In the jtag server source, comment out the dbg_test() procedure call in
  main(). This prevents initialisation of devices not present in this
  design.

* If the or1200_defines.v file is not changed to enable the trace buffer
  (OR1200_DU_TB_IMPLEMENTED), change the gdb source by commenting out the
  call to or1k_read_trace() in remote-or1k.c:or1k_wait().

* Modify the board.h file for orpmon or hello-uart programs to reflect
  the 50MHz clock-speed.