URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
[/] [or1k/] [trunk/] [rc203soc/] [sw/] [uClinux/] [arch/] [or32/] [board/] [rom.ld] - Rev 1777
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MEMORY
{
romvec : ORIGIN = 0xf0000000, LENGTH = 0x2000
flash : ORIGIN = 0xf0002000, LENGTH = 0x00800000 - 0x2000
eflash : ORIGIN = 0xf0800000, LENGTH = 0
ramvec : ORIGIN = 0x00000000, LENGTH = 0x00002000
ram : ORIGIN = 0x00002000, LENGTH = 0x00800000 - 0x2000
eram : ORIGIN = 0x00800000, LENGTH = 0
}
SECTIONS
{
.romvec :
{
__romvec = . ;
*(.romvec)
} > romvec
.text :
{
___rom_start = . ;
text_start = . ;
*(.text)
} > flash
.rodata :
{
*(.rodata)
__etext = . ;
} > flash
.initrd :
{
__initrd_start = . ;
*(.initrd)
__initrd_end = . ;
___data_rom_start = . ;
} > flash
.eflash :
{
__flashend = . ;
} > eflash
.data :
AT ( ADDR (.initrd) + SIZEOF (.initrd))
{
__ramstart = . ;
__sdata = . ;
___data_start = . ;
*(.data)
__edata = . ;
__end_data = . ;
__data_end = . ;
edata = ALIGN( 0x10 ) ;
} > ram
.bss :
{
__sbss = ALIGN( 0x10 ) ;
___bss_start = ALIGN( 0x10 ) ;
*(.bss)
*(COMMON)
__ebss = . ;
___bss_end = . ;
end = ALIGN( 0x10 ) ;
__end = ALIGN( 0x10 ) ;
} > ram
.ramvec :
AT ( ADDR (.initrd) + SIZEOF (.initrd) + SIZEOF (.data))
{
__ramvec_start = . ;
*(.ramvec)
__ramvec_end = . ;
} > ramvec
.eram :
{
__ramend = . ;
} > eram
}
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