URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
[/] [or1k/] [trunk/] [rtems-20020807/] [c/] [src/] [lib/] [libbsp/] [sh/] [gensh4/] [start/] [start.S] - Rev 1765
Compare with Previous | Blame | View Log
/** start.S -- Initialization code for SH7750 generic BSP** Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia* Author: Victor V. Vengerov <vvv@oktet.ru>** Based on work:* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and* Bernd Becker (becker@faw.uni-ulm.de)** COPYRIGHT (c) 1997-1998, FAW Ulm, Germany** This program is distributed in the hope that it will be useful,* but WITHOUT ANY WARRANTY; without even the implied warranty of* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.** Modified to reflect Hitachi EDK SH7045F:* John M. Mills (jmills@tga.com)* TGA Technologies, Inc.* 100 Pinnacle Way, Suite 140* Norcross, GA 30071 U.S.A.*** This modified file may be copied and distributed in accordance* the above-referenced license. It is provided for critique and* developmental purposes without any warranty nor representation* by the authors or by TGA Technologies.** COPYRIGHT (c) 1999-2001.* On-Line Applications Research Corporation (OAR).** The license and distribution terms for this file may be* found in the file LICENSE in this distribution or at* http://www.OARcorp.com/rtems/license.html.** start.S,v 1.1 2001/10/11 19:04:12 joel Exp*/#include "asm.h"#include "rtems/score/sh4_regs.h"#include "rtems/score/sh7750_regs.h"BEGIN_CODEPUBLIC(start)/** Algorithm of the first part of the start():** 1. Initialize stack* 2. Are we from reset or from gdb? Set value for boot_mode in r9.* 3. Initialize hardware if we are from reset. Cache is off.* 4. Copy data from flash to ram; set up boot mode and jump to real address.* 5. Zero out bss.* 6. Turn memory cach on.*/SYM (start):! install the stack pointermov.l stack_k,r15mov.l initial_sr_k,r0ldc r0,ssrldc r0,sr! let us see if we are from gdb stub or from power-on resetbsr fake_funcnopfake_func:sts pr, r0shlr8 r0mov.l reset_pc_value_shift_8_k, r1cmp/eq r0, r1movt r9 ! r9 == ! boot_modeneg r9, r9add #1, r9 ! r9 == boot_mode! what is in boot_mode?cmp/pl r9 ! r9 > 0 -> T = 1! if boot_mode != SH4_BOOT_MODE_FLASHbt hw_init_endnop#if defined(START_HW_INIT) /* from $RTEMS_BSP.cfg */! Initialize minimal hardware! to run hw_init we need to calculate its address! as it is before data copingmov.l hw_init_k, r0mov.l copy_start_k, r1mov.l copy_end_k, r2cmp/ge r0, r1bt 0fcmp/ge r0, r2bf 0f! if copy_start <= hw_init <= copy_end thenneg r1, r1mov.l copy_start_in_rom_k, r3add r1,r0add r3, r00:jsr @r0nop !delay slot#endif /* START_HW_INIT */hw_init_end:! copy data from rom to rammov.l copy_start_k, r0mov.l copy_end_k, r1mov.l copy_start_in_rom_k, r2! if copy_from == copy_to do not copy anythingcmp/eq r0, r2bt real_addressnopcopy_data_cycle:cmp/ge r1, r0bt end_of_copy_data_cyclenopmov.l @r2+, r3mov.l r3, @r0add #4, r0bra copy_data_cyclenopend_of_copy_data_cycle:! go to 0x8....... adressesmov.l real_address_k, r0lds r0, prrtsnopreal_address:! write boot_mode to rammov.l boot_mode_k, r5mov.l r9, @r5zero_bss:! zero out bssmov.l __bss_start_k,r0mov.l __bss_end_k,r1mov #0,r20:mov.l r2,@r0add #4,r0cmp/ge r0,r1bt 0bnop! Turn cache onmov.l cache_on_k, r0jsr @r0nop !delay slot! Save old value of VBR register. We will need it to allow! debugger agent hook exceptions.mov.l __VBR_Saved_k,r0stc vbr,r5mov.l r5,@r0! Set up VBR registermov.l _vbr_base_k,r0ldc r0,vbr! initialise fpscr for gccmov.l set_fpscr_k, r1jsr @r1nop! Set FPSCR registermov.l initial_fpscr_k,r0lds r0,fpscr! call the mainlinemov #0,r4 ! argcmov.l main_k,r0jsr @r0mov #0,r5 ! argv - can place in dead slot! call exitmov r0,r4mov.l exit_k,r0jsr @r0or r0,r0.global _stop_stop:mov #11,r0mov #0,r4trapa #0x3fnop__stop:bra __stopnopEND_CODE.align 2copy_start_k:.long copy_startcopy_end_k:.long copy_endcopy_start_in_rom_k:.long copy_start_in_romreal_address_k:.long real_addressset_fpscr_k:.long ___set_fpscr_vbr_base_k:.long SYM(_vbr_base)__VBR_Saved_k:.long SYM(_VBR_Saved)stack_k:.long SYM(stack)__bss_start_k:.long __bss_start__bss_end_k:.LONG __bss_endmain_k:.long SYM(boot_card)exit_k:.long SYM(_exit)#ifdef START_HW_INIT /* from $RTEMS_BSP.cfg */hw_init_k:.long SYM(early_hw_init)#endif /* START_HW_INIT */cache_on_k:.long SYM(bsp_cache_on)vects_k:.long SYM(vectab)vects_size:.word 255.align 2initial_sr_k:.long SH4_SR_MD | SH4_SR_IMASKinitial_fpscr_k:#ifdef __SH4__.long SH4_FPSCR_DN | SH4_FPSCR_PR | SH4_FPSCR_RM#else.long SH4_FPSCR_DN | SH4_FPSCR_RM#endifreset_pc_value_shift_8_k:.long 0xa00000boot_mode_k:.long _boot_mode#ifdef __ELF__.section .stack,"aw"#else.section .stack#endifSYM(stack):.long 0xdeaddead#ifdef __ELF__.section .bss,"aw"#else.section .bss#endif.global __sh4sim_dummy_register__sh4sim_dummy_register:.long 0.section .data.global _boot_mode_boot_mode:.long 0
