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(*
     Register writeback unit

     Copyright 2004 Ken Rose
     All rights reserved
*)

-T

is

component T +MD +ALU +IR +WriteSelect +MA +SPR -WD
with
  Byte Half
is

{display '0' ({vector_of_string "Insn in WB is " $} '++' {hex_of_vector IR $})}
  Half <- MA'[1] '==' '1' 'then'  MD'[15:0]
      'else'                      MD'[31:16]

  Byte <- {mux MA'[1:0] [MD'[31:24] MD'[23:16] MD'[15:8] MD'[7:0]] $}

  (* Control for writeback mux.  Must match decode
       "0000"   ALU output
       "0001"   Zero-extended memory word
       "0010"   Sign-extended memory word
       "0011"   Zero-extended memory byte
       "0100"   Sign-extended memory byte
       "0101"   Zero-extended memory halfword
       "0110"   Sign-extended memory halfword
       "0111"   Immediate data in high half
       "1000"   Data from SPR
  *)
  {display '0' ({vector_of_string "Memory address is " $} '++' {hex_of_vector MA $})}
  WD <- {mux WriteSelect [ALU 
                           MD
                           MD
                           (('0' '#' 24) '++' Byte)
                           ((Byte'[7] '#' 24) '++' Byte)
                           (('0' '#' 16) '++' Half)
                           ((Half'[15] '#' 16) '++' Half)
                           (IR'[15:0] '++' ('0' '#' 16))
                           SPR
                           ] $}
end