Subversion Repositories or1k_old

This directory includes some test case programs that should be used to verify correct operation
of the or1ksim, OR32 GCC and OR32 GNU Binutils.

All programs are built from root directories. You need to have all GNU OR32 tools installed and in
path.

!!! For all test cases, or1ksim should be built with ONLY_VIRTUAL_MACHINE undefined in 
cpu/or1k/except.h !!!

Dhrystone 2.1: a benchmark modified to use simulator's timing facility. It should finish with exit(0).
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

running simulation:

# ./sim testbench/dhrystone/dhry.or32
(sim) run -1 hush
<cut> <cut> <cut>
MTSPR(0x1234, 20070);
MTSPR(0x1234, 20013);
MTSPR(0x1234, 7);
MTSPR(0x1234, 30010);
MTSPR(0x1234, 30010);
MTSPR(0x1234, 8);
MTSPR(0x1234, 20020);
MTSPR(0x1234, 9);
syscall exit(0)
(sim)

stdout.txt should read like this:

Execution starts, 20 runs through Dhrystone
Begin Time = 549
End Time   = 22701
OR1K at 200 MHz
Microseconds for one run through Dhrystone: 110 us / 20 runs
Dhrystones per Second:                      181

basic: a test for all instructions and all GPRs. If everything is ok, RESULT == 0xdeadead.
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

Simulation:
# ./sim testbench/basic.or32
(sim) run -1 hush
UART 0 RX EOF detected. Shutting down to prevent endless loop.
MTSPR(0x1234, ffff0012);
MTSPR(0x1234, 12352af7);
MTSPR(0x1234, 7ffffffe);
MTSPR(0x1234, ffffa5a7);
MTSPR(0x1234, fffff);
MTSPR(0x1234, 2800);
MTSPR(0x1234, a);
MTSPR(0x1234, deaddead);
syscall exit(0)
(sim)

Standard output:
RESULT: deaddead


test1: a test for "all" instructions and their combinations. If everything is ok, RESULT == 0xdeadead.
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

Simulation:
# ./sim testbench/cbasic.or32
(sim) run -1 hush
MTSPR(0x1234, ffffffda);
MTSPR(0x1234, ffffffc5);
MTSPR(0x1234, 6805);
MTSPR(0x1234, ffff97f9);
MTSPR(0x1234, ffff97f9);
MTSPR(0x1234, 7a77952e);
MTSPR(0x1234, 81e5e000);
MTSPR(0x1234, 74);
MTSPR(0x1234, 74);
MTSPR(0x1234, 74);
MTSPR(0x1234, 1);
MTSPR(0x1234, d7c);
MTSPR(0x1234, 74);
MTSPR(0x1234, 74);
MTSPR(0x1234, 74);
MTSPR(0x1234, ffffffff);
MTSPR(0x1234, d7a);
MTSPR(0x1234, d7a);
MTSPR(0x1234, deaddead);
syscall exit(0)
(sim)

Standard output:
RESULT: deaddead

pic: a test for PIC and TICK timer. All three modes of TICK timer are tested and interrupt is enabled and disabled in PIC. If everything is ok, RESULT == 0xdeadead.
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

Simulation:
# ./sim testbench/pic.or32
(sim) run -1 hush
...
...
...
MTSPR(0x1234, 178);
MTSPR(0x1234, 178);
MTSPR(0x1234, deaddead);
syscall exit(0)
(sim)  

Standard output:
RESULT: deaddead

excpt: a test of l.sys instruction. Checks all the delay slot issues ind other things. If everything is ok, RESULT == 0xdeadead.
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
Simulation:
# ./sim testbench/excpt.or32
(sim) run -1 hush
UART 0 RX EOF detected. Shutting down to prevent endless loop.
Exception 0xc00 (System Call): Iqueue[0].insn_addr: 0xc74  Eff ADDR: 0x0
  pc: 0xc74  pcnext: 0xc78
MTSPR(0x1234, 1);
MTSPR(0x1234, 1);
MTSPR(0x1234, 1c);
MTSPR(0x1234, 1);
MTSPR(0x1234, 3);
MTSPR(0x1234, deaddead);
syscall exit(0)
(sim)    

Standard output:
RESULT: deaddead

cfg: a test of SPRs (SPR_VR, SPR_CPUCFGR, SPR_DMMUCFGR, SPR_IMMUCFGR, SPR_DCCFGR, SPR_ICCFGR, SPR_DCFGR, SPR_PCCFGR). If everything is ok, RESULT == 0xdeadead.
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
Simulation:
# ./sim testbench/cfg.or32
(sim) run -1 hush
MTSPR(0x1234, 0);
MTSPR(0x1234, e83f);
MTSPR(0x1234, 0);
MTSPR(0x1234, 5);
MTSPR(0x1234, 20);
MTSPR(0x1234, 1d);
MTSPR(0x1234, 1d);
MTSPR(0x1234, 1d);
MTSPR(0x1234, 1d);
MTSPR(0x1234, 8);
MTSPR(0x1234, 1);
MTSPR(0x1234, deaddead);
syscall exit(0)
(sim)      

Standard output:
RESULT: deaddead

dma: a test of DMA in normal (software) mode. If everything is ok, RESULT == 0xdeadead.
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
Simulation:
# ./sim testbench/dma.or32
(sim) run 1000000 hush
MTSPR(0x1234, 1);
MTSPR(0x1234, 6);
MTSPR(0x1234, a);
MTSPR(0x1234, deaddead);
syscall exit(0)
(sim)      

Standard output:
RESULT: deaddead

compress: UNIX compressed modified not to use libc calls. Should finish with exit(0).
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

Simulation:

./sim testbench/compress/mycompress.or32
(sim) run -1 hush
Interrupt reported.
Interrupt reported.
syscall exit(0)
(sim)

Standard output:

main: bytes_out 3... hsize 5003
main: hshift 4...
main: bytes_out 3...
main: hsize_reg 5003...
main: before compress 1...
main: compressing 1...
main: compressing 2...
main: compressing 3...
<cut> <cut> <cut>
main: compressing 997...
main: compressing 998...
main: compressing 999...
main: output...
main: end...

mul: Test l.mul, l.mac and l.macrc instructions. Should finish with exit(0).
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Simulation:
./sim testbench/mul.or32
(sim) run -1 hush
MTSPR(0x1234, deadbeef);
syscall exit(0)
(sim)

Standard output:

0xa6312f33, expected 0xa6312f33
0x0d4de375, expected 0x0d4de375
0x61ab48dc, expected 0x61ab48dc
Test succesful.