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#Xilinx CORE Generator 3.1i_ip_update3: Project Manager (Do not edit)
#Mon Aug 20 00:52:10 PDT 2001
synchronous_dram_controller|nmi_electronics_ltd.|xc4000+virtex+spartan2|1.0=active
accumulator|xilinx|virtex_all|1.0=inactive
c8251_programmable_communications_interface|cast_inc.|virtex+spartan2|1.0=active
c16450_universal_asynchronous_receiver_transmitter|cast_inc.|spartan2+virtex|1.0=active
accumulator|xilinx|virtex_all+virtex2|2.0=inactive
accumulator|xilinx|virtex_all+virtex2|3.0=inactive
accumulator|xilinx|virtex_all+virtex2|4.0=active
viewlogiclibraryalias=
numerically_controlled_oscillator|xilinx|xc4000_all+virtex_all|1.1=active
1024-pt_complex_fast_fourier_transform.|xilinx|virtex2|2.0=active
fast_ethernet_mac_core_evaluation_board|coreel_microsystems|xc4000|1.0=active
c2901_microprocessor_slice|cast_inc.|virtex+spartan2|1.0=active
distributed_arithmetic_fir_filter|xilinx|virtex_all+virtex2|5.0=active
distributed_arithmetic_fir_filter|xilinx|virtex_all+virtex2|3.0=inactive
distributed_arithmetic_fir_filter|xilinx|virtex_all+virtex2|4.0=inactive
8x8_multiplier|xilinx|xc4000_all|1.0=active
xilinxfamily=Virtex
three-input_multiplexer|xilinx|xc4000_all|1.0=active
ld-based_parallel_latch|xilinx|virtex_all|1.0=inactive
xf_des_data_encryption_standard_engine_core|memec_design_services|xc4000+spartan|1.0=active
asynchronous_fifo|xilinx|virtex_all+virtex2|3.0=active
asynchronous_fifo|xilinx|virtex_all+virtex2|2.0=inactive
1's_or_2's_complement|xilinx|xc4000_all|1.0=active
des_-_triple_des_cryptoprocessor|xentec,_inc.|virtex+spartan2|1.0=active
can_bus_interface|sican_microelectronics|xc4000|1.0=active
registered_rom|xilinx|xc4000_all|1.0=active
hdlc32|xilinx|virtex+spartan2|1.0=active
sine-cosine_look-up_table|xilinx|xc4000_all+virtex_all|1.0=inactive
fast_ethernet_mac_transmitter_&_receiver|coreel_microsystems|virtex+xc4000+++spartan2|1.0=active
gva-220_dsp_hardware_accelerator|gv_&_associates_inc.|xc4000+spartan|1.0=active
compact_uart|cast_inc.|virtex+spartan2|1.0=active
square_root|xilinx|xc4000_all|1.0=active
mux_slice_bufe|xilinx|virtex_all|1.0=active
64-pt_complex_fast_fourier_transform|xilinx|virtex|1.0=active
fd-based_shift_register|xilinx|virtex_all|1.0=inactive
asynchronous_fifo|xilinx|virtex_all|1.0=inactive
integrator|xilinx|xc4000_all|1.0=active
cascaded_integrator_comb_filter|xilinx|virtex_all+virtex2|1.0=active
multiply_accumulator|xilinx|virtex_all+virtex2|1.1=active
multiply_accumulator|xilinx|virtex_all+virtex2|1.0=inactive
16-pt_complex_fast_fourier_transform|xilinx|virtex|1.0=active
cell_assembler_(cc201)|coreel_microsystems|xc4000|1.0=active
interleaver-deinterleaver|cselt_s.p.a|virtex+spartan+spartan2|1.0=active
designflow=Verilog
fd-based_parallel_register|xilinx|virtex_all+virtex2|4.0=active
fd-based_parallel_register|xilinx|virtex_all+virtex2|3.0=inactive
fd-based_parallel_register|xilinx|virtex_all+virtex2|2.0=inactive
variable_parallel_multiplier|xilinx|virtex_all+virtex2|2.0=active
pci32_spartan_xl_interface|xilinx|spartan|1.0=active
bus_multiplexer|xilinx|virtex_all|1.0=inactive
bit_multiplexer|xilinx|virtex_all|1.0=inactive
fileversion=2
synchronous_fifo|xilinx|virtex_all+virtex2|1.0=inactive
synchronous_fifo|xilinx|virtex_all+virtex2|2.0=active
twos_complementer|xilinx|virtex_all+virtex2|4.0=active
twos_complementer|xilinx|virtex_all+virtex2|3.0=inactive
twos_complementer|xilinx|virtex_all+virtex2|2.0=inactive
dual_port_block_memory|xilinx|virtex2+virtex_all|3.0=inactive
dual_port_block_memory|xilinx|virtex2+virtex_all|3.1=active
sine-cosine_look-up_table|xilinx|virtex_all+virtex2|3.0=active
parallel_to_serial_converter|xilinx|xc4000_all|1.0=active
256-pt_complex_fast_fourier_transform.|xilinx|virtex2|2.0=active
sine-cosine_look-up_table|xilinx|virtex_all|2.1=inactive
sine-cosine_look-up_table|xilinx|virtex_all|2.0=inactive
block_memory_dual_port_virtex_ii|xilinx|virtex2|2.0=active
ima-32_inverse_multiplexer_for_atm|applied_telecom,_inc.|xc4000+virtex|1.0=active
arbiter|cselt_s.p.a|virtex+spartan+spartan2|1.0=active
iss_adpcm|integrated_silicon_systems,_ltd.|virtex+spartan2|1.0=active
xilinx_pci64_plus_64-bit_design_kit|xilinx|virtex|1.0=active
32_point_parameterisable_complex_fast_fourier_transform|xilinx|virtex_all+virtex|1.0=active
busformat=BusFormatParen
vtoolsd_windows_device_driver_development_kit|xilinx|xc4000+spartan|1.0=active
utopia_level-3_atm_transmitter|xentec,_inc.|virtex|1.0=active
utopia_level-3_phy_transmitter|xentec,_inc.|virtex|1.0=active
dvb_satellite_modulator_core|memec_design_services|virtex|1.0=active
xilinx_reed-solomon_encoder|xilinx|virtex_all+xc4000+spartan|1.0=active
xilinx_reed-solomon_decoder|xilinx|virtex_all+xc4000+spartan|1.0=active
symmetric_16_deep_time_skew_buffer|xilinx|xc4000_all|1.0=active
twos_complementer|xilinx|virtex_all|1.0=inactive
pci32_virtex_interface|xilinx|virtex|1.0=active
mt1f_t1_framer|virtual_ip_group,_inc|xc4000|1.0=active
xf8279_programmable_keyboard_display_interface|memec_design_services|xc4000+spartan|1.0=active
adpcm32|xilinx|virtex+spartan2|1.0=active
distributed_memory|xilinx|virtex_all+virtex2|2.0=inactive
distributed_memory|xilinx|virtex_all+virtex2|3.0=inactive
distributed_memory|xilinx|virtex_all+virtex2|4.0=active
pci32_spartan_interface|xilinx|spartan|1.0=active
binary_counter|xilinx|virtex_all|1.0=inactive
iss_reed-solomon_encoder|integrated_silicon_systems,_ltd.|virtex+xc4000+spartan+spartan2|1.0=active
iss_reed-solomon_decoder|integrated_silicon_systems,_ltd.|virtex+xc4000+spartan+spartan2|1.0=active
direct_digital_synthesizer|xilinx|virtex_all+virtex2|3.0=active
v8-urisc_8-bit_risc_microprocessor|vautomation|xc4000|1.0=active
multiplexer_slice_buft|xilinx|virtex_all+virtex2|2.0=inactive
multiplexer_slice_bufe|xilinx|virtex_all+virtex2|2.0=inactive
multiplexer_slice_buft|xilinx|virtex_all+virtex2|3.0=inactive
multiplexer_slice_bufe|xilinx|virtex_all+virtex2|3.0=inactive
multiplexer_slice_buft|xilinx|virtex_all+virtex2|4.0=active
multiplexer_slice_bufe|xilinx|virtex_all+virtex2|4.0=active
gva-270_virtex-e_dsp_hardware_accelerator|gv_&_associates_inc.|virtex|1.0=active
registered_scaled_adder|xilinx|xc4000_all|1.0=active
bit_gate|xilinx|virtex_all|1.0=inactive
bus_gate|xilinx|virtex_all|1.0=inactive
ycrcb_to_rgb|perigee_llc|xc4000|1.0=active
parallel_multiplier_-_area_optimized|xilinx|xc4000_all|1.0=active
cell_delineation_(cc200)|coreel_microsystems|xc4000|1.0=active
d80530_microcontroller|cast_inc.|virtex|1.0=active
pipelined_delay_element|xilinx|xc4000_all|1.0=active
ram-based_shift_register|xilinx|virtex_all+virtex2|4.0=active
ram-based_shift_register|xilinx|virtex_all+virtex2|3.0=inactive
ram-based_shift_register|xilinx|virtex_all+virtex2|2.0=inactive
non-pipelined_constant_coefficient_multiplier|xilinx|xc4000_all|1.0=active
utopia_slave_(cc143s)|coreel_microsystems|virtex+xc4000+spartan+spartan2|1.0=active
distributed_sample_scrambler|cselt_s.p.a|virtex+spartan+spartan2|1.0=active
flip805x-pr_core|dolphin_integration|virtex+spartan2|1.0=active
noisy_transmission_channel_model|cselt_s.p.a|virtex+spartan+spartan2|1.0=active
m8259_programmable_interrupt_controller|virtual_ip_group,_inc|xc4000+spartan|1.0=active
des_cryptoprocessor|xentec,_inc.|virtex+spartan2|1.0=active
decode_8b/10b|xilinx|virtex_all+virtex2|2.0=active
decode_8b/10b|xilinx|virtex_all+virtex2|1.0=inactive
single_port_block_memory|xilinx|virtex_all+virtex2|3.1=active
single_port_block_memory|xilinx|virtex_all+virtex2|3.0=inactive
register|xilinx|xc4000_all|1.0=active
simulationoutputproducts=Verilog
pci32_spartan-ii_interface|xilinx|spartan2|1.0=active
sda_fir_filter|xilinx|xc4000_all|1.0=active
arc_32-bit_configurable_risc_processor|arc_cores|virtex+spartan2|1.0=active
microprocessor-based_core_evaluation_card|nmi_electronics_ltd.|xc4000|1.0=active
multiplier|xilinx|virtex_all+virtex2|3.0=active
multiplier|xilinx|virtex_all+virtex2|2.0=inactive
dynamic_constant_coefficient_multiplier|xilinx|virtex_all|1.0=inactive
non-symmetric_32_deep_time_skew_buffer|xilinx|xc4000_all|1.0=active
corelibraryid=996502259468
m16450_universal_asynchronous_receiver/transmitter|virtual_ip_group,_inc|xc4000+spartan|1.0=active
pipelined_divider|xilinx|xc4000_all+virtex_all+virtex2|2.0=active
adder_subtracter|xilinx|virtex_all+virtex2|4.0=active
adder_subtracter|xilinx|virtex_all+virtex2|3.0=inactive
adder_subtracter|xilinx|virtex_all+virtex2|2.0=inactive
200_mhz_sdram_controller|rapid_prototypes,_inc.|xc4000+virtex+spartan2|1.0=active
xf8255_programmable_peripheral_interface|memec_design_services|xc4000+spartan|1.0=active
12x12_multiplier|xilinx|xc4000_all|1.0=active
viterbi_decoder|cselt_s.p.a|virtex+spartan+spartan2|1.0=active
encode_8b/10b|xilinx|virtex_all+virtex2|1.0=active
m8254_programmable_timer|virtual_ip_group,_inc|virtex+spartan+spartan2|1.0=active
xf8250_asynchronous_communication_core(uart)|memec_design_services|xc4000+spartan|1.0=active
single-channel_xf-hdlc_controller|memec_design_services|xc4000+spartan+virtex+spartan2|1.0=active
fd-based_shift_register|xilinx|virtex_all+virtex2|4.0=active
fd-based_shift_register|xilinx|virtex_all+virtex2|3.0=inactive
fd-based_shift_register|xilinx|virtex_all+virtex2|2.0=inactive
distributed_memory|xilinx|virtex_all|1.0=inactive
crc10_generator_&_verifier_(cc-130)|coreel_microsystems|xc4000+spartan|1.0=active
crc32_generator_&_verifier_(cc-131)|coreel_microsystems|xc4000+spartan|1.0=active
registered_loadable_adder|xilinx|xc4000_all|1.0=active
compact_version_of_d80530_microcontroller|cast_inc.|virtex|1.0=active
registered_subtracter|xilinx|xc4000_all|1.0=active
256-pt_complex_fast_fourier_transform|xilinx|virtex|1.0=active
gva-100_dsp_prototyping_platform|gv_&_associates_inc.|xc4000|1.0=active
xilinx_pci64/66_virtex_interface|xilinx|virtex|1.0=active
utopia_master_(cc140f)|coreel_microsystems|xc4000|1.0=active
utopia_level-3_phy_receiver|xentec,_inc.|virtex|1.0=active
utopia_level-3_atm_receiver|xentec,_inc.|virtex|1.0=active
memec_reed-solomon_encoder|memec_design_services|xc4000+virtex+spartan+spartan2|1.0=active
1024-pt_complex_fast_fourier_transform|xilinx|virtex|1.0=active
gva-250_virtex_dsp_hardware_accelerator|gv_&_associates_inc.|virtex|1.0=active
bit_multiplexer|xilinx|virtex_all+virtex2|2.0=inactive
bus_multiplexer|xilinx|virtex_all+virtex2|2.0=inactive
bit_multiplexer|xilinx|virtex_all+virtex2|3.0=inactive
bus_multiplexer|xilinx|virtex_all+virtex2|3.0=inactive
bit_multiplexer|xilinx|virtex_all+virtex2|4.0=active
bus_multiplexer|xilinx|virtex_all+virtex2|4.0=active
adder_subtracter|xilinx|virtex_all|1.0=inactive
dynamic_constant_coefficient_multiplier|xilinx|virtex_all+virtex2|2.0=active
flowvendor=Exemplar
registered_loadable_subtracter|xilinx|xc4000_all|1.0=active
two-input_multiplexer|xilinx|xc4000_all|1.0=active
variable_parallel_multiplier|xilinx|virtex_all|1.0=inactive
registered_dualport_ram|xilinx|xc4000_all|1.0=active
registered_serial_adder|xilinx|xc4000_all|1.0=active
distributed_sample_descrambler|cselt_s.p.a|virtex+spartan+spartan2|1.0=active
xf8256_multifunction_microprocessor_support_controller|memec_design_services|xc4000+spartan|1.0=active
c8259a_programmable_interrupt_controller|cast_inc.|virtex+spartan2|1.0=active
dct-idct_forward_and_inverse_discrete_cosine_transform|xentec,_inc.|virtex+spartan2|1.0=active
multiplexer_slice_buft|xilinx|virtex_all|1.0=inactive
dual_channel_numerically_controlled_oscillator|xilinx|xc4000_all+virtex_all|1.1=active
comparator|xilinx|virtex_all|1.0=inactive
registered_singleport_ram|xilinx|xc4000_all|1.0=active
gva-200a_dsp_hardware_accelerator|gv_&_associates_inc.|xc4000+spartan|1.0=active
registered_adder|xilinx|xc4000_all|1.0=active
64-pt_complex_fast_fourier_transform.|xilinx|virtex2|2.0=active
utopia_slave_(cc141)|coreel_microsystems|xc4000|1.0=active
rgb2ycrcb_color_space_converter|perigee_llc|xc4000+spartan+virtex+spartan2|1.0=active
bus_gate|xilinx|virtex_all+virtex2|4.0=active
bit_gate|xilinx|virtex_all+virtex2|4.0=active
bus_gate|xilinx|virtex_all+virtex2|3.0=inactive
bit_gate|xilinx|virtex_all+virtex2|3.0=inactive
bus_gate|xilinx|virtex_all+virtex2|2.0=inactive
bit_gate|xilinx|virtex_all+virtex2|2.0=inactive
fd-based_parallel_register|xilinx|virtex_all|1.0=inactive
binary_decoder|xilinx|virtex_all|1.0=inactive
distributed_arithmetic_fir_filter|xilinx|virtex_all|1.0=inactive
binary_counter|xilinx|virtex_all+virtex2|2.0=inactive
binary_counter|xilinx|virtex_all+virtex2|3.0=inactive
binary_counter|xilinx|virtex_all+virtex2|4.0=active
scaled_by_one-half_accumulator|xilinx|xc4000_all|1.0=active
block_memory_single_port_virtex_ii|xilinx|virtex2|2.0=active
pci64/66_spartan-ii_interface|xilinx|spartan2|1.0=active
pipelined_divider|xilinx|xc4000_all+virtex_all|1.0=inactive
ppp8_hdlc|coreel_microsystems|xc4000+virtex+spartan2|1.0=active
parallel_distributed_arithmetic_fir_filter|xilinx|xc4000_all|1.0=active
bit_bus_gate|xilinx|virtex_all+virtex2|2.0=inactive
bit_bus_gate|xilinx|virtex_all+virtex2|3.0=inactive
bit_bus_gate|xilinx|virtex_all+virtex2|4.0=active
m16550a_universal_asynchronous_receiver/transmitter_with_fifos|virtual_ip_group,_inc|xc4000+spartan|1.0=active
single_port_block_memory|xilinx|virtex+spartan2|1.0=inactive
jpeg_codec|xentec,_inc.|virtex|1.0=active
non-symmetric_16_deep_time_skew_buffer|xilinx|xc4000_all|1.0=active
c8255a_peripheral_interface|cast_inc.|virtex+spartan2|1.0=active
c16550_universal_asynchronous_receiver_transmitter_with_fifos|cast_inc.|spartan2+virtex|1.0=active
pipelined_constant_coefficient_multiplier|xilinx|xc4000_all|1.0=active
bit_correlator|xilinx|virtex_all+virtex2|2.0=active
convolutional_encoder|cselt_s.p.a|virtex+spartan+spartan2|1.0=active
16-pt_complex_fast_fourier_transform.|xilinx|virtex2|2.0=active
utopia_level-2_phy_side_rx_interface|cselt_s.p.a|virtex+spartan+spartan2|1.0=active
utopia_level-2_phy_side_tx_interface|cselt_s.p.a|virtex+spartan+spartan2|1.0=active
hdlc1|xilinx|virtex+spartan2|1.0=active
longitudinal_time_code_generator|deltatec|xc4000+virtex|1.0=active
m8237_dma_controller|virtual_ip_group,_inc|xc4000|1.0=active
ycrcb2rgb_color_space_converter|perigee_llc|xc4000+spartan+virtex+spartan2|1.0=active
xf-twsi_two-wire_serial_interface_master|memec_design_services|xc4000+spartan|1.0=active
ld-based_parallel_latch|xilinx|virtex_all+virtex2|4.0=active
ld-based_parallel_latch|xilinx|virtex_all+virtex2|3.0=inactive
ld-based_parallel_latch|xilinx|virtex_all+virtex2|2.0=inactive
c6850_asynchronous_communications_interface_adapter|cast_inc.|spartan2+virtex|1.0=active
synchronous_fifo|xilinx|xc4000_all|1.0=inactive
four-input_multiplexer|xilinx|xc4000_all|1.0=active
m8255_programmable_peripheral_interface|virtual_ip_group,_inc|virtex+spartan+spartan2|1.0=active
dual_port_block_memory|xilinx|virtex+spartan2|1.0=inactive
ima-8_inverse_multiplexer_for_atm|applied_telecom,_inc.|spartan2|1.0=active
content_addressable_memory|xilinx|virtex_all+virtex2|1.0=active
c2910a_microprogram_controller|cast_inc.|virtex+xc4000+spartan|1.0=active
binary_decoder|xilinx|virtex_all+virtex2|2.0=inactive
binary_decoder|xilinx|virtex_all+virtex2|3.0=inactive
binary_decoder|xilinx|virtex_all+virtex2|4.0=active
comb_filter|xilinx|xc4000_all|1.0=active
8051_compatible_high-speed_8-bit_risc_microcontroller|cast_inc.|virtex|1.0=active
ram-based_shift_register|xilinx|virtex_all|1.0=inactive
xf-twsi-ms_two-wire_serial_interface_master-slave|memec_design_services|virtex+spartan2+xc4000+spartan|1.0=active
comparator|xilinx|virtex_all+virtex2|2.0=inactive
comparator|xilinx|virtex_all+virtex2|3.0=inactive
comparator|xilinx|virtex_all+virtex2|4.0=active
memec_reed-solomon_decoder|memec_design_services|virtex+xc4000+spartan2|1.0=active
intellicore_prototyping_system|vautomation|xc4000|1.0=active
bit_bus_gate|xilinx|virtex_all|1.0=inactive
direct_digital_synthesizer|xilinx|virtex_all|2.0=inactive