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// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/MUXCY_D.v,v 1.1.1.1 2001-11-04 18:59:49 lampret Exp $ /* FUNCTION : 2 to 1 Multiplexer for Carry Logic */ `timescale 100 ps / 10 ps `celldefine module MUXCY_D (O, LO, CI, DI, S); parameter cds_action = "ignore"; output O, LO; reg o_out, lo_out; input CI, DI, S; buf B1 (O, o_out); buf B2 (LO, lo_out); always @(CI or DI or S) begin if (S) o_out <= CI; else o_out <= DI; end always @(CI or DI or S) begin if (S) lo_out <= CI; else lo_out <= DI; end specify (CI => O) = (1, 1); (DI => O) = (1, 1); (S => O) = (1, 1); (CI => LO) = (1, 1); (DI => LO) = (1, 1); (S => LO) = (1, 1); endspecify endmodule `endcelldefine