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// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/MUXCY_L.v,v 1.1.1.1 2001-11-04 18:59:49 lampret Exp $
 
/*
 
FUNCTION	: 2 to 1 Multiplexer for Carry Logic
 
*/
 
`timescale  100 ps / 10 ps
 
`celldefine
 
module MUXCY_L (LO, CI, DI, S);
 
    parameter cds_action = "ignore";
 
    output LO;
    reg    lo_out;
 
    input  CI, DI, S;
 
    buf B1 (LO, lo_out);
 
	always @(CI or DI or S) begin
	    if (S)
		lo_out <= CI;
	    else
		lo_out <= DI;
	end
 
    specify
	(CI => LO) = (1, 1);
	(DI => LO) = (1, 1);
	(S  => LO) = (1, 1);
    endspecify
 
endmodule
 
`endcelldefine