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What is this stuff?
===================

This is OpenRISC 1000 architectural simulator. See the file COPYING
for copying permission. To contact the authors, see AUTHORS file.

This simulator loads an assembly file for one of the both architectures
and it simulates the operation of instructions. 

Installation
============

To compile, run the configure script and specify the target architecture.
Example:

  $ ./configure --target=or32

After that, just issue "make all" command. By default there should be no
warnings. There is no "make install". Just use it from default location
or copy it to your bin directory (usually something like /usr/local/bin
or ~/bin).

GNU Tools
=========

Instructions how to build GNU tools can be found on www.opencores.org

Simulator test
==============

Edit the sim.cfg file in order to configure your system.

Issue 'sim testbench/dhry.or32' or 'sim testbench/dhry.dlx' to
test simulator. See testbench/README for more details about running.

Also run sim with --help option for list of command line options and
help in command mode, to list the commands.

OpenRISC and open cores
=======================

About the same idea as with GNU project except we want free and open source
IP (intellectual property) cores. We design open source, synthesizable
cores. OpenRISC is one such core. It is a 32-bit RISC microprocessor that
will run GNU/Linux.
For more information visit us at http://www.opencores.org.