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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Ethernet Interface for RC203 board                          ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Manages access from Wishbone to Ethernet SMC91111 Chip      ////
////                                                              ////
////  To Do:                                                      ////
////   - nothing really                                           ////
////                                                              ////
////  Author(s):                                                  ////
////      - Javier Castillo, javier.castillo@urjc.es              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2005 OpenCores                                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2005/05/26 12:25:42  jcastillo
// Added support for ethernet chip
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module wb_eth_controller(clk,reset,
 
                         wb_stb_i,wb_dat_o,wb_dat_i,
                         wb_ack_o,wb_adr_i,wb_we_i,
                         wb_cyc_i,wb_sel_i,
 
                         eth_nREAD,eth_nWRITE,eth_address,eth_data,
                         eth_nBE,eth_reset
                        );
 
input         clk;
input         reset;
//
// WISHBONE INTERFACE
//
input         wb_stb_i;
output [31:0] wb_dat_o;
input  [31:0] wb_dat_i;
output        wb_ack_o;
input  [31:0] wb_adr_i;
input         wb_we_i;
input         wb_cyc_i;
input  [3:0]  wb_sel_i;
 
//
// SMC91111 PINS
//
output        eth_nREAD;
output        eth_nWRITE;
output [2:0]  eth_address;
inout  [15:0] eth_data;   //INOUT
output [1:0]  eth_nBE;
output        eth_reset;
 
reg  [31:0]   wb_dat_o;
reg           wb_ack_o;
reg           eth_nREAD;
reg           eth_nWRITE;
reg  [2:0]    eth_address;
reg  [1:0]    eth_nBE;
wire [15:0]   eth_data;
wire          eth_ardy;
wire          eth_reset;
 
reg   next_reading;
reg   reading;
reg   next_writing;
reg   writing;
 
//State Machine
parameter IDLE=0,
          ACTIVE_STROBE=1;
 
 
reg [1:0] state,next_state;
reg [4:0] counter,next_counter;
reg [31:0] next_wb_dat_o;
reg [15:0] half_word;
 
reg [7:0] bytes[8:0];
 
assign eth_reset = reset;
assign eth_data = (next_writing | writing) ? half_word : 16'hZ;
 
always @(wb_adr_i or wb_stb_i or wb_sel_i or wb_ack_o or wb_we_i or wb_cyc_i or counter
         or reading or writing or wb_ack_o or state or wb_dat_o or eth_data or wb_dat_i)
 
   begin
 
   next_wb_dat_o=wb_dat_o;
 
   next_reading  = reading;
   next_writing  = writing;
 
   next_state=state;
   next_counter=counter;
 
   eth_address  = wb_adr_i[3:1];   
 
   eth_nREAD  = 1'b1;
   eth_nWRITE = 1'b1;
 
   //Allocate the data in correct position for writes
   half_word=16'h0;
 
   bytes[1]=wb_dat_i[7:0];
   bytes[2]=wb_dat_i[15:8];
   bytes[4]=wb_dat_i[23:16];
   bytes[8]=wb_dat_i[31:24];
 
   //Byte write
   eth_nBE[0]=wb_adr_i[0];
   eth_nBE[1]=~wb_adr_i[0];
   case(wb_adr_i[0])
     1'b1:
     begin
       half_word[15:8]=bytes[wb_sel_i];
     end
     1'b0:
	 begin
     half_word[7:0]=bytes[wb_sel_i];
     end
   endcase 
 
   //Word write
   case(wb_sel_i)
     4'b0011:
     begin
      eth_nBE=2'b00;
      half_word=wb_dat_i[15:0];
     end
     4'b1100:
     begin
      eth_nBE=2'b00;
      half_word=wb_dat_i[31:16];
     end
	 default:
	 begin
	 end
   endcase
 
   case(state) 
      IDLE:
      begin
        if (wb_cyc_i && wb_stb_i && !wb_we_i && !wb_ack_o)
        begin
          //Single memory read 
          next_reading  = 1'b1;
          next_writing  = 1'b0;
          next_state=ACTIVE_STROBE;
		  eth_nBE=2'b00;	 //Read Always 16 bits
        end
        else if (wb_cyc_i && wb_stb_i && wb_we_i && !wb_ack_o)
        begin
          //Single memory write
          next_writing  = 1'b1; 
          next_reading  = 1'b0;
          next_state=ACTIVE_STROBE;
        end
      end
      ACTIVE_STROBE:
      begin
        if(reading)
		begin
		  eth_nBE=2'b00;	 //Read Always 16 bits
          eth_nREAD=1'b0;
		end
        else if (writing)
		begin
          eth_nWRITE=1'b0;
		end
        if(counter==5)
        begin
          next_state=IDLE;
          next_counter=0;
          eth_nREAD=1'b1;
          eth_nWRITE=1'b1;		
          next_writing=1'b0;
          next_reading=1'b0;
        end
        else if(counter==4 && reading)
        begin
          next_counter=counter+1;
  	       next_wb_dat_o=32'b0;
		  case(wb_sel_i)
		    //Reallocate bits for wishbone
		    4'b0001:
			begin
              next_wb_dat_o[7:0]=eth_data[15:8];
			end
		    4'b0010:
			begin
              next_wb_dat_o[15:8]=eth_data[7:0];
			end
  	        4'b0100:
			begin
              next_wb_dat_o[23:16]=eth_data[15:8];
			end
     	    4'b1000:
  		    begin
              next_wb_dat_o[31:24]=eth_data[7:0];
		    end
		    4'b0011:
		    begin
              next_wb_dat_o[15:0]=eth_data;
		    end
		    4'b1100:
		    begin
              next_wb_dat_o[31:16]=eth_data;
		    end
			4'b1111:
			begin
			  next_wb_dat_o[15:0]=16'hDEAD;
			end
	    endcase
        end
        else
        begin
          next_counter=counter+1;
        end
      end 
 
   endcase   
 
 end
 
 
//register_proc:
always @(posedge clk or posedge reset)
 
   begin
 
   if (reset )
      begin
      state    <= #1 0;
      counter  <= #1 0;
      reading  <= #1 1'b0;
      writing  <= #1 1'b0;
      wb_ack_o <= #1 1'b0;
      wb_dat_o <= #1 32'h0;
      end
   else 
      begin
      state    <= #1 next_state;
      counter  <= #1 next_counter;
      writing  <= #1 next_writing;
      reading  <= #1 next_reading;
      wb_dat_o <= #1  next_wb_dat_o;
      if((reading | writing) && counter==5)
        wb_ack_o<= #1 1'b1;
      else
        wb_ack_o<= #1 1'b0;
      end
   end
 
endmodule