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[/] [or1k_old/] [trunk/] [rc203soc/] [rtl/] [verilog/] [uart16550/] [bench/] [verilog/] [vapi.log] - Rev 1782
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////////////////////////////////////////////////////////////////////////// //////// vapi.log //////// //////// //////// This file is part of the "UART 16550 compatible" project //////// http://www.opencores.org/projects/uart16550/ //////// //////// Documentation related to this project: //////// http://www.opencores.org/projects/uart16550/ //////// //////// Projects compatibility: //////// - WISHBONE //////// RS232 Protocol //////// 16550D uart (mostly supported) //////// //////// Overview (main Features): //////// Device interface for testing purposes //////// //////// Known problems (limits): //////// //////// To Do: //////// Nothing. //////// //////// Author(s): //////// - Igor Mohor (igorm@opencores.org) //////// //////// Created and updated: (See log for the revision history) //////// //////// ////////////////////////////////////////////////////////////////////////////// //////// Copyright (C) 2001 Authors //////// //////// This source file may be used and distributed without //////// restriction provided that this copyright statement is not //////// removed from the file and that any derivative work contains //////// the original copyright notice and the associated disclaimer. //////// //////// This source file is free software; you can redistribute it //////// and/or modify it under the terms of the GNU Lesser General //////// Public License as published by the Free Software Foundation; //////// either version 2.1 of the License, or (at your option) any //////// later version. //////// //////// This source is distributed in the hope that it will be //////// useful, but WITHOUT ANY WARRANTY; without even the implied //////// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //////// PURPOSE. See the GNU Lesser General Public License for more //////// details. //////// //////// You should have received a copy of the GNU Lesser General //////// Public License along with this source; if not, download it //////// from http://www.opencores.org/lgpl.shtml //////// ////////////////////////////////////////////////////////////////////////////// CVS Revision History//// $Log: not supported by cvs2svn $// Revision 1.1 2002/01/25 08:54:56 mohor// UART PHY added. Files are fully operational, working on HW.//////////001000020 // devisor 0x32002000300 // rx lcr 8n1// Receive10000034a // Receive J100000361 // Receive a100000363 // Receive c10000030a // Receive \n// Send000000371 // Transmit q - switching to interrupt mode100000353 // Receive S100000377 // Receive w10000030a // Receive \n006000020 // wait 32 tx cycles000000331 // Transmit 1000000332 // Transmit 2000000333 // Transmit 3000000334 // Transmit 4000000335 // Transmit 5000000336 // Transmit 6000000337 // Transmit 7000000338 // Transmit 8000000339 // Transmit 9000000361 // Transmit a000000362 // Transmit b000000363 // Transmit c000000364 // Transmit d000000365 // Transmit e000000366 // Transmit f006000040 // wait 64 tx cycles100000331 // Receive 1100000332 // Receive 2100000333 // Receive 3100000334 // Receive 4100000335 // Receive 5100000336 // Receive 6100000337 // Receive 7100000338 // Receive 8100000339 // Receive 9100000341 // Receive A100000342 // Receive B100000343 // Receive C100000344 // Receive D100000345 // Receive E100000346 // Receive F200000000 // Exit simulation