OpenCores
URL https://opencores.org/ocsvn/or1k_soc_on_altera_embedded_dev_kit/or1k_soc_on_altera_embedded_dev_kit/trunk

Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [linux-2.6/] [linux-2.6.24/] [arch/] [or32/] [README.or32] - Rev 7

Compare with Previous | Blame | View Log

This is a port of Linux to OpenRISC 1000 family of microprocessors. 

Changes:
18. 11. 2003    Matjaz Breskvar (phoenix@bsemi.com)
        initial port of linux to OpenRISC/or32 architecture. 
        all the core stuff is implemented and seams usable.

08. 12. 2003    Matjaz Breskvar (phoenix@bsemi.com)
        complete change of TLB miss handling.
        rewrite of exceptions handling.
        fully functional sash-3.6 in default initrd.
        a much improved version with changes all around.

10. 04. 2004    Matjaz Breskvar (phoenix@bsemi.com)
        alot of bugfixes all over.
        ethernet support, functional http and telnet servers.
        running many standard linux apps.

26. 06. 2004    Matjaz Breskvar (phoenix@bsemi.com)
        port to 2.6.x

30. 11. 2004    Matjaz Breskvar (phoenix@bsemi.com)
        lots of bugfixes and enhancments.
        added opencores framebuffer driver.

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.