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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [linux-2.6/] [linux-2.6.24/] [include/] [asm-or32/] [cacheflush.h] - Rev 7
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#ifndef _OR32_CACHEFLUSH_H #define _OR32_CACHEFLUSH_H /* Keep includes the same across arches. */ #include <linux/mm.h> /* The cache doesn't need to be flushed when TLB entries change because * the cache is mapped to physical memory, not virtual memory */ #define flush_cache_all() do { } while (0) #define flush_cache_mm(mm) do { } while (0) #define flush_cache_dup_mm(mm) do { } while (0) #define flush_cache_range(vma, start, end) do { } while (0) #define flush_cache_page(vma, vmaddr, pfn) do { } while (0) #define flush_dcache_page(page) do { } while (0) #define flush_dcache_mmap_lock(mapping) do { } while (0) #define flush_dcache_mmap_unlock(mapping) do { } while (0) #define flush_icache_range(start, end) do { } while (0) #define flush_icache_page(vma,pg) do { } while (0) #define flush_icache_user_range(vma,pg,adr,len) do { } while (0) #define flush_cache_vmap(start, end) do { } while (0) #define flush_cache_vunmap(start, end) do { } while (0) #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ memcpy(dst, src, len) #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ memcpy(dst, src, len) void global_flush_tlb(void); int change_page_attr(struct page *page, int numpages, pgprot_t prot); #endif /* _OR32_CACHEFLUSH_H */