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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [prj/] [altera/] [altera_ram_top_tb.v] - Rev 12
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// Copyright (C) 1991-2009 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // ***************************************************************************** // This file contains a Verilog test bench with test vectors .The test vectors // are exported from a vector file in the Quartus Waveform Editor and apply to // the top level entity of the current Quartus project .The user can use this // testbench to simulate his design using a third-party simulation tool . // ***************************************************************************** // Generated on "10/07/2009 15:47:19" // Verilog Self-Checking Test Bench (with test vectors) for design : altera_ram_top // // Simulation tool : 3rd Party // `timescale 1 ps/ 1 ps module altera_ram_top_vlg_sample_tst( wb_adr_i, wb_clk_i, wb_cyc_i, wb_dat_i, wb_rst_i, wb_sel_i, wb_stb_i, wb_we_i, sampler_tx ); input [31:0] wb_adr_i; input wb_clk_i; input wb_cyc_i; input [31:0] wb_dat_i; input wb_rst_i; input [3:0] wb_sel_i; input wb_stb_i; input wb_we_i; output sampler_tx; reg sample; time current_time; always @(wb_adr_i or wb_clk_i or wb_cyc_i or wb_dat_i or wb_rst_i or wb_sel_i or wb_stb_i or wb_we_i) begin if ($time > 0) begin if ($time == 0 || $time != current_time) begin if (sample === 1'bx) sample = 0; else sample = ~sample; end current_time = $time; end end assign sampler_tx = sample; endmodule module altera_ram_top_vlg_check_tst ( wb_ack_o,wb_dat_o,wb_err_o,sampler_rx ); input wb_ack_o; input [31:0] wb_dat_o; input wb_err_o; input sampler_rx; reg wb_ack_o_expected; reg [31:0] wb_dat_o_expected; reg wb_err_o_expected; reg wb_ack_o_prev; reg [31:0] wb_dat_o_prev; reg wb_err_o_prev; reg wb_ack_o_expected_prev; reg [31:0] wb_dat_o_expected_prev; reg wb_err_o_expected_prev; reg last_wb_ack_o_exp; reg [31:0] last_wb_dat_o_exp; reg last_wb_err_o_exp; reg trigger; integer i; integer nummismatches; reg [1:3] on_first_change ; initial begin trigger = 0; i = 0; nummismatches = 0; on_first_change = 3'b1; end // update real /o prevs always @(trigger) begin wb_ack_o_prev = wb_ack_o; wb_dat_o_prev = wb_dat_o; wb_err_o_prev = wb_err_o; end // update expected /o prevs always @(trigger) begin wb_ack_o_expected_prev = wb_ack_o_expected; wb_dat_o_expected_prev = wb_dat_o_expected; wb_err_o_expected_prev = wb_err_o_expected; end // expected wb_ack_o initial begin wb_ack_o_expected = 1'bX; end // expected wb_dat_o[ 31 ] initial begin wb_dat_o_expected[31] = 1'bX; end // expected wb_dat_o[ 30 ] initial begin wb_dat_o_expected[30] = 1'bX; end // expected wb_dat_o[ 29 ] initial begin wb_dat_o_expected[29] = 1'bX; end // expected wb_dat_o[ 28 ] initial begin wb_dat_o_expected[28] = 1'bX; end // expected wb_dat_o[ 27 ] initial begin wb_dat_o_expected[27] = 1'bX; end // expected wb_dat_o[ 26 ] initial begin wb_dat_o_expected[26] = 1'bX; end // expected wb_dat_o[ 25 ] initial begin wb_dat_o_expected[25] = 1'bX; end // expected wb_dat_o[ 24 ] initial begin wb_dat_o_expected[24] = 1'bX; end // expected wb_dat_o[ 23 ] initial begin wb_dat_o_expected[23] = 1'bX; end // expected wb_dat_o[ 22 ] initial begin wb_dat_o_expected[22] = 1'bX; end // expected wb_dat_o[ 21 ] initial begin wb_dat_o_expected[21] = 1'bX; end // expected wb_dat_o[ 20 ] initial begin wb_dat_o_expected[20] = 1'bX; end // expected wb_dat_o[ 19 ] initial begin wb_dat_o_expected[19] = 1'bX; end // expected wb_dat_o[ 18 ] initial begin wb_dat_o_expected[18] = 1'bX; end // expected wb_dat_o[ 17 ] initial begin wb_dat_o_expected[17] = 1'bX; end // expected wb_dat_o[ 16 ] initial begin wb_dat_o_expected[16] = 1'bX; end // expected wb_dat_o[ 15 ] initial begin wb_dat_o_expected[15] = 1'bX; end // expected wb_dat_o[ 14 ] initial begin wb_dat_o_expected[14] = 1'bX; end // expected wb_dat_o[ 13 ] initial begin wb_dat_o_expected[13] = 1'bX; end // expected wb_dat_o[ 12 ] initial begin wb_dat_o_expected[12] = 1'bX; end // expected wb_dat_o[ 11 ] initial begin wb_dat_o_expected[11] = 1'bX; end // expected wb_dat_o[ 10 ] initial begin wb_dat_o_expected[10] = 1'bX; end // expected wb_dat_o[ 9 ] initial begin wb_dat_o_expected[9] = 1'bX; end // expected wb_dat_o[ 8 ] initial begin wb_dat_o_expected[8] = 1'bX; end // expected wb_dat_o[ 7 ] initial begin wb_dat_o_expected[7] = 1'bX; end // expected wb_dat_o[ 6 ] initial begin wb_dat_o_expected[6] = 1'bX; end // expected wb_dat_o[ 5 ] initial begin wb_dat_o_expected[5] = 1'bX; end // expected wb_dat_o[ 4 ] initial begin wb_dat_o_expected[4] = 1'bX; end // expected wb_dat_o[ 3 ] initial begin wb_dat_o_expected[3] = 1'bX; end // expected wb_dat_o[ 2 ] initial begin wb_dat_o_expected[2] = 1'bX; end // expected wb_dat_o[ 1 ] initial begin wb_dat_o_expected[1] = 1'bX; end // expected wb_dat_o[ 0 ] initial begin wb_dat_o_expected[0] = 1'bX; end // expected wb_err_o initial begin wb_err_o_expected = 1'bX; end // generate trigger always @(wb_ack_o_expected or wb_ack_o or wb_dat_o_expected or wb_dat_o or wb_err_o_expected or wb_err_o) begin trigger <= ~trigger; end always @(posedge sampler_rx or negedge sampler_rx) begin `ifdef debug_tbench $display("Scanning pattern %d @time = %t",i,$realtime ); i = i + 1; $display("| expected wb_ack_o = %b | expected wb_dat_o = %b | expected wb_err_o = %b | ",wb_ack_o_expected_prev,wb_dat_o_expected_prev,wb_err_o_expected_prev); $display("| real wb_ack_o = %b | real wb_dat_o = %b | real wb_err_o = %b | ",wb_ack_o_prev,wb_dat_o_prev,wb_err_o_prev); `endif if ( ( wb_ack_o_expected_prev !== 1'bx ) && ( wb_ack_o_prev !== wb_ack_o_expected_prev ) && ((wb_ack_o_expected_prev !== last_wb_ack_o_exp) || on_first_change[1]) ) begin $display ("ERROR! Vector Mismatch for output port wb_ack_o :: @time = %t", $realtime); $display (" Expected value = %b", wb_ack_o_expected_prev); $display (" Real value = %b", wb_ack_o_prev); nummismatches = nummismatches + 1; on_first_change[1] = 1'b0; last_wb_ack_o_exp = wb_ack_o_expected_prev; end if ( ( wb_dat_o_expected_prev[0] !== 1'bx ) && ( wb_dat_o_prev[0] !== wb_dat_o_expected_prev[0] ) && ((wb_dat_o_expected_prev[0] !== last_wb_dat_o_exp[0]) || on_first_change[2]) ) begin $display ("ERROR! Vector Mismatch for output port wb_dat_o[0] :: @time = %t", $realtime); $display (" Expected value = %b", wb_dat_o_expected_prev); $display (" Real value = %b", wb_dat_o_prev); nummismatches = nummismatches + 1; on_first_change[2] = 1'b0; last_wb_dat_o_exp[0] = wb_dat_o_expected_prev[0]; end if ( ( wb_dat_o_expected_prev[1] !== 1'bx ) && ( wb_dat_o_prev[1] !== wb_dat_o_expected_prev[1] ) && ((wb_dat_o_expected_prev[1] !== last_wb_dat_o_exp[1]) || on_first_change[2]) ) begin $display ("ERROR! Vector Mismatch for output port wb_dat_o[1] :: @time = %t", $realtime); $display (" Expected value = %b", wb_dat_o_expected_prev); $display (" Real value = %b", wb_dat_o_prev); nummismatches = nummismatches + 1; on_first_change[2] = 1'b0; last_wb_dat_o_exp[1] = wb_dat_o_expected_prev[1]; end if ( ( wb_dat_o_expected_prev[2] !== 1'bx ) && ( wb_dat_o_prev[2] !== wb_dat_o_expected_prev[2] ) && ((wb_dat_o_expected_prev[2] !== last_wb_dat_o_exp[2]) || on_first_change[2]) ) begin $display ("ERROR! Vector Mismatch for output port wb_dat_o[2] :: @time = %t", $realtime); $display (" Expected value = %b", wb_dat_o_expected_prev); $display (" Real value = %b", wb_dat_o_prev); nummismatches = nummismatches + 1; on_first_change[2] = 1'b0; last_wb_dat_o_exp[2] = wb_dat_o_expected_prev[2]; end if ( ( wb_dat_o_expected_prev[3] !== 1'bx ) && ( wb_dat_o_prev[3] !== wb_dat_o_expected_prev[3] ) && ((wb_dat_o_expected_prev[3] !== last_wb_dat_o_exp[3]) || on_first_change[2]) ) begin $display ("ERROR! Vector Mismatch for output port wb_dat_o[3] :: @time = %t", $realtime); $display (" Expected value = %b", wb_dat_o_expected_prev); $display (" Real value = %b", wb_dat_o_prev); nummismatches = nummismatches + 1; on_first_change[2] = 1'b0; last_wb_dat_o_exp[3] = wb_dat_o_expected_prev[3]; end if ( ( wb_dat_o_expected_prev[4] !== 1'bx ) && ( wb_dat_o_prev[4] !== wb_dat_o_expected_prev[4] ) && ((wb_dat_o_expected_prev[4] !== last_wb_dat_o_exp[4]) || on_first_change[2]) ) begin $display ("ERROR! Vector Mismatch for output port wb_dat_o[4] :: @time = %t", $realtime); $display (" Expected value = %b", wb_dat_o_expected_prev); $display (" Real value = %b", wb_dat_o_prev); nummismatches = nummismatches + 1; on_first_change[2] = 1'b0; last_wb_dat_o_exp[4] = wb_dat_o_expected_prev[4]; end if ( ( wb_dat_o_expected_prev[5] !== 1'bx ) && ( wb_dat_o_prev[5] !== wb_dat_o_expected_prev[5] ) && ((wb_dat_o_expected_prev[5] !== last_wb_dat_o_exp[5]) || on_first_change[2]) ) begin $display ("ERROR! Vector Mismatch for output port wb_dat_o[5] :: @time = %t", $realtime); $display (" Expected value = %b", wb_dat_o_expected_prev); $display (" Real value = %b", wb_dat_o_prev); nummismatches = nummismatches + 1; on_first_change[2] = 1'b0; last_wb_dat_o_exp[5] = wb_dat_o_expected_prev[5]; end if ( ( wb_dat_o_expected_prev[6] !== 1'bx ) && ( wb_dat_o_prev[6] !== wb_dat_o_expected_prev[6] ) && ((wb_dat_o_expected_prev[6] !== last_wb_dat_o_exp[6]) || on_first_change[2]) ) begin $display ("ERROR! Vector Mismatch for output port wb_dat_o[6] :: @time = %t", $realtime); $display (" Expected value = %b", wb_dat_o_expected_prev); $display (" Real value = %b", wb_dat_o_prev); nummismatches = nummismatches + 1; on_first_change[2] = 1'b0; last_wb_dat_o_exp[6] = wb_dat_o_expected_prev[6]; end if ( ( wb_dat_o_expected_prev[7] !== 1'bx ) && ( wb_dat_o_prev[7] !== wb_dat_o_expected_prev[7] ) && ((wb_dat_o_expected_prev[7] !== last_wb_dat_o_exp[7]) || on_first_change[2]) ) begin $display ("ERROR! Vector Mismatch for output port wb_dat_o[7] :: @time = %t", $realtime); $display (" Expected value = %b", wb_dat_o_expected_prev); $display (" Real value = %b", wb_dat_o_prev); nummismatches = nummismatches + 1; on_first_change[2] = 1'b0; last_wb_dat_o_exp[7] = wb_dat_o_expected_prev[7]; end if ( ( wb_dat_o_expected_prev[8] !== 1'bx ) && ( wb_dat_o_prev[8] !== wb_dat_o_expected_prev[8] ) && ((wb_dat_o_expected_prev[8] !== last_wb_dat_o_exp[8]) || on_first_change[2]) ) begin $display ("ERROR! Vector Mismatch for output port wb_dat_o[8] :: @time = %t", $realtime); $display (" Expected value = %b", wb_dat_o_expected_prev); $display (" Real value = %b", wb_dat_o_prev); nummismatches = nummismatches + 1; on_first_change[2] = 1'b0; last_wb_dat_o_exp[8] = wb_dat_o_expected_prev[8]; end if ( ( wb_dat_o_expected_prev[9] !== 1'bx ) && ( wb_dat_o_prev[9] !== wb_dat_o_expected_prev[9] ) && ((wb_dat_o_expected_prev[9] !== last_wb_dat_o_exp[9]) || on_first_change[2]) ) begin $display ("ERROR! Vector Mismatch for output port wb_dat_o[9] :: @time = %t", $realtime); $display (" Expected value = %b", wb_dat_o_expected_prev); $display (" Real value = %b", wb_dat_o_prev); nummismatches = nummismatches + 1; on_first_change[2] = 1'b0; last_wb_dat_o_exp[9] = wb_dat_o_expected_prev[9]; end if ( ( wb_dat_o_expected_prev[10] !== 1'bx ) && ( wb_dat_o_prev[10] !== wb_dat_o_expected_prev[10] ) && ((wb_dat_o_expected_prev[10] !== last_wb_dat_o_exp[10]) || on_first_change[2]) ) begin $display ("ERROR! Vector Mismatch for output port wb_dat_o[10] :: @time = %t", $realtime); $display (" Expected value = %b", wb_dat_o_expected_prev); $display (" Real value = %b", wb_dat_o_prev); nummismatches = nummismatches + 1; on_first_change[2] = 1'b0; last_wb_dat_o_exp[10] = wb_dat_o_expected_prev[10]; end if ( ( wb_dat_o_expected_prev[11] !== 1'bx ) && ( wb_dat_o_prev[11] !== wb_dat_o_expected_prev[11] ) && ((wb_dat_o_expected_prev[11] !== last_wb_dat_o_exp[11]) || on_first_change[2]) ) begin $display ("ERROR! Vector Mismatch for output port wb_dat_o[11] :: @time = %t", $realtime); $display (" Expected value = %b", wb_dat_o_expected_prev); $display (" Real value = %b", wb_dat_o_prev); nummismatches = nummismatches + 1; on_first_change[2] = 1'b0; last_wb_dat_o_exp[11] = wb_dat_o_expected_prev[11]; end if ( ( wb_dat_o_expected_prev[12] !== 1'bx ) && ( wb_dat_o_prev[12] !== wb_dat_o_expected_prev[12] ) && ((wb_dat_o_expected_prev[12] !== last_wb_dat_o_exp[12]) || on_first_change[2]) ) begin $display ("ERROR! Vector Mismatch for output port wb_dat_o[12] :: @time = %t", $realtime); $display (" Expected value = %b", wb_dat_o_expected_prev); $display (" Real value = %b", wb_dat_o_prev); nummismatches = nummismatches + 1; on_first_change[2] = 1'b0; last_wb_dat_o_exp[12] = wb_dat_o_expected_prev[12]; end if ( ( wb_dat_o_expected_prev[13] !== 1'bx ) && ( wb_dat_o_prev[13] !== wb_dat_o_expected_prev[13] ) && ((wb_dat_o_expected_prev[13] !== last_wb_dat_o_exp[13]) || on_first_change[2]) ) begin $display ("ERROR! Vector Mismatch for output port wb_dat_o[13] :: @time = %t", $realtime); $display (" Expected value = %b", wb_dat_o_expected_prev); $display (" Real value = %b", wb_dat_o_prev); nummismatches = nummismatches + 1; on_first_change[2] = 1'b0; last_wb_dat_o_exp[13] = wb_dat_o_expected_prev[13]; end if ( ( wb_dat_o_expected_prev[14] !== 1'bx ) && ( wb_dat_o_prev[14] !== wb_dat_o_expected_prev[14] ) && ((wb_dat_o_expected_prev[14] !== last_wb_dat_o_exp[14]) || on_first_change[2]) ) begin $display ("ERROR! Vector Mismatch for output port wb_dat_o[14] :: @time = %t", $realtime); $display (" Expected value = %b", wb_dat_o_expected_prev); $display (" Real value = %b", wb_dat_o_prev); nummismatches = nummismatches + 1; on_first_change[2] = 1'b0; last_wb_dat_o_exp[14] = wb_dat_o_expected_prev[14]; end if ( ( wb_dat_o_expected_prev[15] !== 1'bx ) && ( wb_dat_o_prev[15] !== wb_dat_o_expected_prev[15] ) && ((wb_dat_o_expected_prev[15] !== last_wb_dat_o_exp[15]) || on_first_change[2]) ) begin $display ("ERROR! Vector Mismatch for output port wb_dat_o[15] :: @time = %t", $realtime); $display (" Expected value = %b", wb_dat_o_expected_prev); $display (" Real value = %b", wb_dat_o_prev); nummismatches = nummismatches + 1; on_first_change[2] = 1'b0; last_wb_dat_o_exp[15] = wb_dat_o_expected_prev[15]; end if ( ( wb_dat_o_expected_prev[16] !== 1'bx ) && ( wb_dat_o_prev[16] !== wb_dat_o_expected_prev[16] ) && ((wb_dat_o_expected_prev[16] !== last_wb_dat_o_exp[16]) || on_first_change[2]) ) begin $display ("ERROR! Vector Mismatch for output port wb_dat_o[16] :: @time = %t", $realtime); $display (" Expected value = %b", wb_dat_o_expected_prev); $display (" Real value = %b", wb_dat_o_prev); nummismatches = nummismatches + 1; on_first_change[2] = 1'b0; last_wb_dat_o_exp[16] = wb_dat_o_expected_prev[16]; end if ( ( wb_dat_o_expected_prev[17] !== 1'bx ) && ( wb_dat_o_prev[17] !== wb_dat_o_expected_prev[17] ) && ((wb_dat_o_expected_prev[17] !== last_wb_dat_o_exp[17]) || on_first_change[2]) ) begin $display ("ERROR! Vector Mismatch for output port wb_dat_o[17] :: @time = %t", $realtime); $display (" Expected value = %b", wb_dat_o_expected_prev); $display (" Real value = %b", wb_dat_o_prev); nummismatches = nummismatches + 1; on_first_change[2] = 1'b0; last_wb_dat_o_exp[17] = wb_dat_o_expected_prev[17]; end if ( ( wb_dat_o_expected_prev[18] !== 1'bx ) && ( wb_dat_o_prev[18] !== wb_dat_o_expected_prev[18] ) && ((wb_dat_o_expected_prev[18] !== last_wb_dat_o_exp[18]) || on_first_change[2]) ) begin $display ("ERROR! Vector Mismatch for output port wb_dat_o[18] :: @time = %t", $realtime); $display (" Expected value = %b", wb_dat_o_expected_prev); $display (" Real value = %b", wb_dat_o_prev); nummismatches = nummismatches + 1; on_first_change[2] = 1'b0; last_wb_dat_o_exp[18] = wb_dat_o_expected_prev[18]; end if ( ( wb_dat_o_expected_prev[19] !== 1'bx ) && ( wb_dat_o_prev[19] !== wb_dat_o_expected_prev[19] ) && ((wb_dat_o_expected_prev[19] !== last_wb_dat_o_exp[19]) || on_first_change[2]) ) begin $display ("ERROR! Vector Mismatch for output port wb_dat_o[19] :: @time = %t", $realtime); $display (" Expected value = %b", wb_dat_o_expected_prev); $display (" Real value = %b", wb_dat_o_prev); nummismatches = nummismatches + 1; on_first_change[2] = 1'b0; last_wb_dat_o_exp[19] = wb_dat_o_expected_prev[19]; end if ( ( wb_dat_o_expected_prev[20] !== 1'bx ) && ( wb_dat_o_prev[20] !== wb_dat_o_expected_prev[20] ) && ((wb_dat_o_expected_prev[20] !== last_wb_dat_o_exp[20]) || on_first_change[2]) ) begin $display ("ERROR! Vector Mismatch for output port wb_dat_o[20] :: @time = %t", $realtime); $display (" Expected value = %b", wb_dat_o_expected_prev); $display (" Real value = %b", wb_dat_o_prev); nummismatches = nummismatches + 1; on_first_change[2] = 1'b0; last_wb_dat_o_exp[20] = wb_dat_o_expected_prev[20]; end if ( ( wb_dat_o_expected_prev[21] !== 1'bx ) && ( wb_dat_o_prev[21] !== wb_dat_o_expected_prev[21] ) && ((wb_dat_o_expected_prev[21] !== last_wb_dat_o_exp[21]) || on_first_change[2]) ) begin $display ("ERROR! Vector Mismatch for output port wb_dat_o[21] :: @time = %t", $realtime); $display (" Expected value = %b", wb_dat_o_expected_prev); $display (" Real value = %b", wb_dat_o_prev); nummismatches = nummismatches + 1; on_first_change[2] = 1'b0; last_wb_dat_o_exp[21] = wb_dat_o_expected_prev[21]; end if ( ( wb_dat_o_expected_prev[22] !== 1'bx ) && ( wb_dat_o_prev[22] !== wb_dat_o_expected_prev[22] ) && ((wb_dat_o_expected_prev[22] !== last_wb_dat_o_exp[22]) || on_first_change[2]) ) begin $display ("ERROR! Vector Mismatch for output port wb_dat_o[22] :: @time = %t", $realtime); $display (" Expected value = %b", wb_dat_o_expected_prev); $display (" Real value = %b", wb_dat_o_prev); nummismatches = nummismatches + 1; on_first_change[2] = 1'b0; last_wb_dat_o_exp[22] = wb_dat_o_expected_prev[22]; end if ( ( wb_dat_o_expected_prev[23] !== 1'bx ) && ( wb_dat_o_prev[23] !== wb_dat_o_expected_prev[23] ) && ((wb_dat_o_expected_prev[23] !== last_wb_dat_o_exp[23]) || on_first_change[2]) ) begin $display ("ERROR! Vector Mismatch for output port wb_dat_o[23] :: @time = %t", $realtime); $display (" Expected value = %b", wb_dat_o_expected_prev); $display (" Real value = %b", wb_dat_o_prev); nummismatches = nummismatches + 1; on_first_change[2] = 1'b0; last_wb_dat_o_exp[23] = wb_dat_o_expected_prev[23]; end if ( ( wb_dat_o_expected_prev[24] !== 1'bx ) && ( wb_dat_o_prev[24] !== wb_dat_o_expected_prev[24] ) && ((wb_dat_o_expected_prev[24] !== last_wb_dat_o_exp[24]) || on_first_change[2]) ) begin $display ("ERROR! Vector Mismatch for output port wb_dat_o[24] :: @time = %t", $realtime); $display (" Expected value = %b", wb_dat_o_expected_prev); $display (" Real value = %b", wb_dat_o_prev); nummismatches = nummismatches + 1; on_first_change[2] = 1'b0; last_wb_dat_o_exp[24] = wb_dat_o_expected_prev[24]; end if ( ( wb_dat_o_expected_prev[25] !== 1'bx ) && ( wb_dat_o_prev[25] !== wb_dat_o_expected_prev[25] ) && ((wb_dat_o_expected_prev[25] !== last_wb_dat_o_exp[25]) || on_first_change[2]) ) begin $display ("ERROR! Vector Mismatch for output port wb_dat_o[25] :: @time = %t", $realtime); $display (" Expected value = %b", wb_dat_o_expected_prev); $display (" Real value = %b", wb_dat_o_prev); nummismatches = nummismatches + 1; on_first_change[2] = 1'b0; last_wb_dat_o_exp[25] = wb_dat_o_expected_prev[25]; end if ( ( wb_dat_o_expected_prev[26] !== 1'bx ) && ( wb_dat_o_prev[26] !== wb_dat_o_expected_prev[26] ) && ((wb_dat_o_expected_prev[26] !== last_wb_dat_o_exp[26]) || on_first_change[2]) ) begin $display ("ERROR! Vector Mismatch for output port wb_dat_o[26] :: @time = %t", $realtime); $display (" Expected value = %b", wb_dat_o_expected_prev); $display (" Real value = %b", wb_dat_o_prev); nummismatches = nummismatches + 1; on_first_change[2] = 1'b0; last_wb_dat_o_exp[26] = wb_dat_o_expected_prev[26]; end if ( ( wb_dat_o_expected_prev[27] !== 1'bx ) && ( wb_dat_o_prev[27] !== wb_dat_o_expected_prev[27] ) && ((wb_dat_o_expected_prev[27] !== last_wb_dat_o_exp[27]) || on_first_change[2]) ) begin $display ("ERROR! Vector Mismatch for output port wb_dat_o[27] :: @time = %t", $realtime); $display (" Expected value = %b", wb_dat_o_expected_prev); $display (" Real value = %b", wb_dat_o_prev); nummismatches = nummismatches + 1; on_first_change[2] = 1'b0; last_wb_dat_o_exp[27] = wb_dat_o_expected_prev[27]; end if ( ( wb_dat_o_expected_prev[28] !== 1'bx ) && ( wb_dat_o_prev[28] !== wb_dat_o_expected_prev[28] ) && ((wb_dat_o_expected_prev[28] !== last_wb_dat_o_exp[28]) || on_first_change[2]) ) begin $display ("ERROR! Vector Mismatch for output port wb_dat_o[28] :: @time = %t", $realtime); $display (" Expected value = %b", wb_dat_o_expected_prev); $display (" Real value = %b", wb_dat_o_prev); nummismatches = nummismatches + 1; on_first_change[2] = 1'b0; last_wb_dat_o_exp[28] = wb_dat_o_expected_prev[28]; end if ( ( wb_dat_o_expected_prev[29] !== 1'bx ) && ( wb_dat_o_prev[29] !== wb_dat_o_expected_prev[29] ) && ((wb_dat_o_expected_prev[29] !== last_wb_dat_o_exp[29]) || on_first_change[2]) ) begin $display ("ERROR! Vector Mismatch for output port wb_dat_o[29] :: @time = %t", $realtime); $display (" Expected value = %b", wb_dat_o_expected_prev); $display (" Real value = %b", wb_dat_o_prev); nummismatches = nummismatches + 1; on_first_change[2] = 1'b0; last_wb_dat_o_exp[29] = wb_dat_o_expected_prev[29]; end if ( ( wb_dat_o_expected_prev[30] !== 1'bx ) && ( wb_dat_o_prev[30] !== wb_dat_o_expected_prev[30] ) && ((wb_dat_o_expected_prev[30] !== last_wb_dat_o_exp[30]) || on_first_change[2]) ) begin $display ("ERROR! Vector Mismatch for output port wb_dat_o[30] :: @time = %t", $realtime); $display (" Expected value = %b", wb_dat_o_expected_prev); $display (" Real value = %b", wb_dat_o_prev); nummismatches = nummismatches + 1; on_first_change[2] = 1'b0; last_wb_dat_o_exp[30] = wb_dat_o_expected_prev[30]; end if ( ( wb_dat_o_expected_prev[31] !== 1'bx ) && ( wb_dat_o_prev[31] !== wb_dat_o_expected_prev[31] ) && ((wb_dat_o_expected_prev[31] !== last_wb_dat_o_exp[31]) || on_first_change[2]) ) begin $display ("ERROR! Vector Mismatch for output port wb_dat_o[31] :: @time = %t", $realtime); $display (" Expected value = %b", wb_dat_o_expected_prev); $display (" Real value = %b", wb_dat_o_prev); nummismatches = nummismatches + 1; on_first_change[2] = 1'b0; last_wb_dat_o_exp[31] = wb_dat_o_expected_prev[31]; end if ( ( wb_err_o_expected_prev !== 1'bx ) && ( wb_err_o_prev !== wb_err_o_expected_prev ) && ((wb_err_o_expected_prev !== last_wb_err_o_exp) || on_first_change[3]) ) begin $display ("ERROR! Vector Mismatch for output port wb_err_o :: @time = %t", $realtime); $display (" Expected value = %b", wb_err_o_expected_prev); $display (" Real value = %b", wb_err_o_prev); nummismatches = nummismatches + 1; on_first_change[3] = 1'b0; last_wb_err_o_exp = wb_err_o_expected_prev; end trigger <= ~trigger; end initial begin $timeformat(-12,3," ps",6); #2000000; if (nummismatches > 0) $display ("%d mismatched vectors : Simulation failed !",nummismatches); else $display ("Simulation passed !"); $stop; end endmodule module altera_ram_top_vlg_vec_tst(); // constants // general purpose registers reg [31:0] wb_adr_i; reg wb_clk_i; reg wb_cyc_i; reg [31:0] wb_dat_i; reg wb_rst_i; reg [3:0] wb_sel_i; reg wb_stb_i; reg wb_we_i; // wires wire wb_ack_o; wire [31:0] wb_dat_o; wire wb_err_o; wire sampler; // assign statements (if any) altera_ram_top i1 ( // port map - connection between master ports and signals/registers .wb_ack_o(wb_ack_o), .wb_adr_i(wb_adr_i), .wb_clk_i(wb_clk_i), .wb_cyc_i(wb_cyc_i), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o), .wb_err_o(wb_err_o), .wb_rst_i(wb_rst_i), .wb_sel_i(wb_sel_i), .wb_stb_i(wb_stb_i), .wb_we_i(wb_we_i) ); // wb_clk_i always begin wb_clk_i = 1'b0; wb_clk_i = #10000 1'b1; #10000; end // wb_rst_i initial begin wb_rst_i = 1'b0; wb_rst_i = #20000 1'b1; wb_rst_i = #20000 1'b0; wb_rst_i = #980000 1'b1; wb_rst_i = #20000 1'b0; end // wb_adr_i[ 31 ] initial begin wb_adr_i[31] = 1'b0; end // wb_adr_i[ 30 ] initial begin wb_adr_i[30] = 1'b0; end // wb_adr_i[ 29 ] initial begin wb_adr_i[29] = 1'b0; end // wb_adr_i[ 28 ] initial begin wb_adr_i[28] = 1'b0; end // wb_adr_i[ 27 ] initial begin wb_adr_i[27] = 1'b0; end // wb_adr_i[ 26 ] initial begin wb_adr_i[26] = 1'b0; end // wb_adr_i[ 25 ] initial begin wb_adr_i[25] = 1'b0; end // wb_adr_i[ 24 ] initial begin wb_adr_i[24] = 1'b0; end // wb_adr_i[ 23 ] initial begin wb_adr_i[23] = 1'b0; end // wb_adr_i[ 22 ] initial begin wb_adr_i[22] = 1'b0; end // wb_adr_i[ 21 ] initial begin wb_adr_i[21] = 1'b0; end // wb_adr_i[ 20 ] initial begin wb_adr_i[20] = 1'b0; end // wb_adr_i[ 19 ] initial begin wb_adr_i[19] = 1'b0; end // wb_adr_i[ 18 ] initial begin wb_adr_i[18] = 1'b0; end // wb_adr_i[ 17 ] initial begin wb_adr_i[17] = 1'b0; end // wb_adr_i[ 16 ] initial begin wb_adr_i[16] = 1'b0; end // wb_adr_i[ 15 ] initial begin wb_adr_i[15] = 1'b0; end // wb_adr_i[ 14 ] initial begin wb_adr_i[14] = 1'b0; end // wb_adr_i[ 13 ] initial begin wb_adr_i[13] = 1'b0; end // wb_adr_i[ 12 ] initial begin wb_adr_i[12] = 1'b0; end // wb_adr_i[ 11 ] initial begin wb_adr_i[11] = 1'b0; end // wb_adr_i[ 10 ] initial begin wb_adr_i[10] = 1'b0; end // wb_adr_i[ 9 ] initial begin wb_adr_i[9] = 1'b0; end // wb_adr_i[ 8 ] initial begin wb_adr_i[8] = 1'b1; end // wb_adr_i[ 7 ] initial begin wb_adr_i[7] = 1'b0; end // wb_adr_i[ 6 ] initial begin wb_adr_i[6] = 1'b0; end // wb_adr_i[ 5 ] initial begin wb_adr_i[5] = 1'b0; wb_adr_i[5] = #640000 1'b1; wb_adr_i[5] = #80000 1'b0; wb_adr_i[5] = #80000 1'b1; wb_adr_i[5] = #200000 1'b0; wb_adr_i[5] = #640000 1'b1; wb_adr_i[5] = #80000 1'b0; wb_adr_i[5] = #80000 1'b1; end // wb_adr_i[ 4 ] initial begin wb_adr_i[4] = 1'b0; wb_adr_i[4] = #320000 1'b1; wb_adr_i[4] = #320000 1'b0; wb_adr_i[4] = #80000 1'b1; wb_adr_i[4] = #80000 1'b0; wb_adr_i[4] = #160000 1'b1; wb_adr_i[4] = #40000 1'b0; wb_adr_i[4] = #320000 1'b1; wb_adr_i[4] = #160000 1'b0; wb_adr_i[4] = #80000 1'b1; wb_adr_i[4] = #80000 1'b0; wb_adr_i[4] = #80000 1'b1; wb_adr_i[4] = #80000 1'b0; wb_adr_i[4] = #160000 1'b1; end // wb_adr_i[ 3 ] initial begin repeat(2) begin wb_adr_i[3] = 1'b0; wb_adr_i[3] = #160000 1'b1; # 160000; end wb_adr_i[3] = 1'b0; wb_adr_i[3] = #80000 1'b1; wb_adr_i[3] = #240000 1'b0; wb_adr_i[3] = #200000 1'b1; wb_adr_i[3] = #160000 1'b0; wb_adr_i[3] = #240000 1'b1; wb_adr_i[3] = #80000 1'b0; wb_adr_i[3] = #160000 1'b1; wb_adr_i[3] = #160000 1'b0; end // wb_adr_i[ 2 ] initial begin repeat(4) begin wb_adr_i[2] = 1'b0; wb_adr_i[2] = #80000 1'b1; # 80000; end wb_adr_i[2] = 1'b0; wb_adr_i[2] = #240000 1'b1; wb_adr_i[2] = #80000 1'b0; wb_adr_i[2] = #120000 1'b1; wb_adr_i[2] = #80000 1'b0; wb_adr_i[2] = #80000 1'b1; wb_adr_i[2] = #80000 1'b0; wb_adr_i[2] = #80000 1'b1; wb_adr_i[2] = #240000 1'b0; wb_adr_i[2] = #80000 1'b1; wb_adr_i[2] = #80000 1'b0; wb_adr_i[2] = #80000 1'b1; wb_adr_i[2] = #80000 1'b0; end // wb_adr_i[ 1 ] initial begin wb_adr_i[1] = 1'b0; end // wb_adr_i[ 0 ] initial begin wb_adr_i[0] = 1'b0; end // wb_sel_i[ 3 ] initial begin wb_sel_i[3] = 1'b1; wb_sel_i[3] = #1080000 1'b0; wb_sel_i[3] = #50000 1'b1; end // wb_sel_i[ 2 ] initial begin wb_sel_i[2] = 1'b1; wb_sel_i[2] = #1080000 1'b0; wb_sel_i[2] = #50000 1'b1; end // wb_sel_i[ 1 ] initial begin wb_sel_i[1] = 1'b1; end // wb_sel_i[ 0 ] initial begin wb_sel_i[0] = 1'b1; wb_sel_i[0] = #1080000 1'b0; wb_sel_i[0] = #50000 1'b1; end // wb_stb_i initial begin wb_stb_i = 1'b0; wb_stb_i = #80000 1'b1; wb_stb_i = #50000 1'b0; wb_stb_i = #120000 1'b1; wb_stb_i = #40000 1'b0; wb_stb_i = #200000 1'b1; wb_stb_i = #40000 1'b0; wb_stb_i = #200000 1'b1; wb_stb_i = #40000 1'b0; wb_stb_i = #310000 1'b1; wb_stb_i = #50000 1'b0; wb_stb_i = #360000 1'b1; wb_stb_i = #40000 1'b0; wb_stb_i = #200000 1'b1; wb_stb_i = #40000 1'b0; end // wb_cyc_i initial begin wb_cyc_i = 1'b0; wb_cyc_i = #80000 1'b1; wb_cyc_i = #50000 1'b0; wb_cyc_i = #120000 1'b1; wb_cyc_i = #40000 1'b0; wb_cyc_i = #200000 1'b1; wb_cyc_i = #40000 1'b0; wb_cyc_i = #200000 1'b1; wb_cyc_i = #40000 1'b0; wb_cyc_i = #310000 1'b1; wb_cyc_i = #50000 1'b0; wb_cyc_i = #360000 1'b1; wb_cyc_i = #40000 1'b0; wb_cyc_i = #200000 1'b1; wb_cyc_i = #40000 1'b0; end // wb_we_i initial begin wb_we_i = 1'b0; wb_we_i = #490000 1'b1; wb_we_i = #40000 1'b0; wb_we_i = #550000 1'b1; wb_we_i = #50000 1'b0; end // wb_dat_i[ 31 ] initial begin wb_dat_i[31] = 1'b0; wb_dat_i[31] = #480000 1'b1; wb_dat_i[31] = #50000 1'b0; wb_dat_i[31] = #550000 1'b1; wb_dat_i[31] = #50000 1'b0; wb_dat_i[31] = #350000 1'b1; wb_dat_i[31] = #50000 1'b0; end // wb_dat_i[ 30 ] initial begin wb_dat_i[30] = 1'b0; wb_dat_i[30] = #1080000 1'b1; wb_dat_i[30] = #50000 1'b0; end // wb_dat_i[ 29 ] initial begin wb_dat_i[29] = 1'b0; wb_dat_i[29] = #480000 1'b1; wb_dat_i[29] = #50000 1'b0; wb_dat_i[29] = #550000 1'b1; wb_dat_i[29] = #50000 1'b0; wb_dat_i[29] = #350000 1'b1; wb_dat_i[29] = #50000 1'b0; end // wb_dat_i[ 28 ] initial begin wb_dat_i[28] = 1'b0; wb_dat_i[28] = #1080000 1'b1; wb_dat_i[28] = #50000 1'b0; end // wb_dat_i[ 27 ] initial begin wb_dat_i[27] = 1'b0; wb_dat_i[27] = #480000 1'b1; wb_dat_i[27] = #50000 1'b0; wb_dat_i[27] = #550000 1'b1; wb_dat_i[27] = #50000 1'b0; wb_dat_i[27] = #350000 1'b1; wb_dat_i[27] = #50000 1'b0; end // wb_dat_i[ 26 ] initial begin wb_dat_i[26] = 1'b0; wb_dat_i[26] = #1080000 1'b1; wb_dat_i[26] = #50000 1'b0; end // wb_dat_i[ 25 ] initial begin wb_dat_i[25] = 1'b0; wb_dat_i[25] = #480000 1'b1; wb_dat_i[25] = #50000 1'b0; wb_dat_i[25] = #550000 1'b1; wb_dat_i[25] = #50000 1'b0; wb_dat_i[25] = #350000 1'b1; wb_dat_i[25] = #50000 1'b0; end // wb_dat_i[ 24 ] initial begin wb_dat_i[24] = 1'b0; wb_dat_i[24] = #480000 1'b1; wb_dat_i[24] = #50000 1'b0; wb_dat_i[24] = #950000 1'b1; wb_dat_i[24] = #50000 1'b0; end // wb_dat_i[ 23 ] initial begin wb_dat_i[23] = 1'b0; wb_dat_i[23] = #480000 1'b1; wb_dat_i[23] = #50000 1'b0; wb_dat_i[23] = #550000 1'b1; wb_dat_i[23] = #50000 1'b0; wb_dat_i[23] = #350000 1'b1; wb_dat_i[23] = #50000 1'b0; end // wb_dat_i[ 22 ] initial begin wb_dat_i[22] = 1'b0; wb_dat_i[22] = #480000 1'b1; wb_dat_i[22] = #50000 1'b0; wb_dat_i[22] = #550000 1'b1; wb_dat_i[22] = #50000 1'b0; wb_dat_i[22] = #350000 1'b1; wb_dat_i[22] = #50000 1'b0; end // wb_dat_i[ 21 ] initial begin wb_dat_i[21] = 1'b0; end // wb_dat_i[ 20 ] initial begin wb_dat_i[20] = 1'b0; wb_dat_i[20] = #1080000 1'b1; wb_dat_i[20] = #50000 1'b0; end // wb_dat_i[ 19 ] initial begin wb_dat_i[19] = 1'b0; wb_dat_i[19] = #480000 1'b1; wb_dat_i[19] = #50000 1'b0; wb_dat_i[19] = #550000 1'b1; wb_dat_i[19] = #50000 1'b0; wb_dat_i[19] = #350000 1'b1; wb_dat_i[19] = #50000 1'b0; end // wb_dat_i[ 18 ] initial begin wb_dat_i[18] = 1'b0; wb_dat_i[18] = #480000 1'b1; wb_dat_i[18] = #50000 1'b0; wb_dat_i[18] = #550000 1'b1; wb_dat_i[18] = #50000 1'b0; wb_dat_i[18] = #350000 1'b1; wb_dat_i[18] = #50000 1'b0; end // wb_dat_i[ 17 ] initial begin wb_dat_i[17] = 1'b0; end // wb_dat_i[ 16 ] initial begin wb_dat_i[16] = 1'b0; wb_dat_i[16] = #480000 1'b1; wb_dat_i[16] = #50000 1'b0; wb_dat_i[16] = #950000 1'b1; wb_dat_i[16] = #50000 1'b0; end // wb_dat_i[ 15 ] initial begin wb_dat_i[15] = 1'b0; wb_dat_i[15] = #480000 1'b1; wb_dat_i[15] = #50000 1'b0; wb_dat_i[15] = #550000 1'b1; wb_dat_i[15] = #50000 1'b0; wb_dat_i[15] = #350000 1'b1; wb_dat_i[15] = #50000 1'b0; end // wb_dat_i[ 14 ] initial begin wb_dat_i[14] = 1'b0; wb_dat_i[14] = #480000 1'b1; wb_dat_i[14] = #50000 1'b0; wb_dat_i[14] = #950000 1'b1; wb_dat_i[14] = #50000 1'b0; end // wb_dat_i[ 13 ] initial begin wb_dat_i[13] = 1'b0; wb_dat_i[13] = #480000 1'b1; wb_dat_i[13] = #50000 1'b0; wb_dat_i[13] = #550000 1'b1; wb_dat_i[13] = #50000 1'b0; wb_dat_i[13] = #350000 1'b1; wb_dat_i[13] = #50000 1'b0; end // wb_dat_i[ 12 ] initial begin wb_dat_i[12] = 1'b0; wb_dat_i[12] = #1080000 1'b1; wb_dat_i[12] = #50000 1'b0; end // wb_dat_i[ 11 ] initial begin wb_dat_i[11] = 1'b0; wb_dat_i[11] = #480000 1'b1; wb_dat_i[11] = #50000 1'b0; wb_dat_i[11] = #550000 1'b1; wb_dat_i[11] = #50000 1'b0; wb_dat_i[11] = #350000 1'b1; wb_dat_i[11] = #50000 1'b0; end // wb_dat_i[ 10 ] initial begin wb_dat_i[10] = 1'b0; wb_dat_i[10] = #480000 1'b1; wb_dat_i[10] = #50000 1'b0; wb_dat_i[10] = #950000 1'b1; wb_dat_i[10] = #50000 1'b0; end // wb_dat_i[ 9 ] initial begin wb_dat_i[9] = 1'b0; wb_dat_i[9] = #480000 1'b1; wb_dat_i[9] = #50000 1'b0; wb_dat_i[9] = #550000 1'b1; wb_dat_i[9] = #50000 1'b0; wb_dat_i[9] = #350000 1'b1; wb_dat_i[9] = #50000 1'b0; end // wb_dat_i[ 8 ] initial begin wb_dat_i[8] = 1'b0; wb_dat_i[8] = #480000 1'b1; wb_dat_i[8] = #50000 1'b0; wb_dat_i[8] = #950000 1'b1; wb_dat_i[8] = #50000 1'b0; end // wb_dat_i[ 7 ] initial begin wb_dat_i[7] = 1'b0; wb_dat_i[7] = #480000 1'b1; wb_dat_i[7] = #50000 1'b0; wb_dat_i[7] = #550000 1'b1; wb_dat_i[7] = #50000 1'b0; wb_dat_i[7] = #350000 1'b1; wb_dat_i[7] = #50000 1'b0; end // wb_dat_i[ 6 ] initial begin wb_dat_i[6] = 1'b0; end // wb_dat_i[ 5 ] initial begin wb_dat_i[5] = 1'b0; end // wb_dat_i[ 4 ] initial begin wb_dat_i[4] = 1'b0; wb_dat_i[4] = #480000 1'b1; wb_dat_i[4] = #50000 1'b0; wb_dat_i[4] = #550000 1'b1; wb_dat_i[4] = #50000 1'b0; wb_dat_i[4] = #350000 1'b1; wb_dat_i[4] = #50000 1'b0; end // wb_dat_i[ 3 ] initial begin wb_dat_i[3] = 1'b0; wb_dat_i[3] = #480000 1'b1; wb_dat_i[3] = #50000 1'b0; wb_dat_i[3] = #550000 1'b1; wb_dat_i[3] = #50000 1'b0; wb_dat_i[3] = #350000 1'b1; wb_dat_i[3] = #50000 1'b0; end // wb_dat_i[ 2 ] initial begin wb_dat_i[2] = 1'b0; end // wb_dat_i[ 1 ] initial begin wb_dat_i[1] = 1'b0; end // wb_dat_i[ 0 ] initial begin wb_dat_i[0] = 1'b0; end altera_ram_top_vlg_sample_tst tb_sample ( .wb_adr_i(wb_adr_i), .wb_clk_i(wb_clk_i), .wb_cyc_i(wb_cyc_i), .wb_dat_i(wb_dat_i), .wb_rst_i(wb_rst_i), .wb_sel_i(wb_sel_i), .wb_stb_i(wb_stb_i), .wb_we_i(wb_we_i), .sampler_tx(sampler) ); altera_ram_top_vlg_check_tst tb_out( .wb_ack_o(wb_ack_o), .wb_dat_o(wb_dat_o), .wb_err_o(wb_err_o), .sampler_rx(sampler) ); endmodule