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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [adv_debug_sys/] [Hardware/] [xilinx_internal_jtag/] [rtl/] [verilog/] [xilinx_internal_jtag_options.v] - Rev 21
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// Xilinx has a different HDL entity for the internal JTAG in each of these. // How thoughtful. //`define SPARTAN2 //`define SPARTAN3 // This is also used for SPARTAN 3E devices //`define SPARTAN3A //`define VIRTEX //`define VIRTEX2 // Also used for the VIRTEX 2P `define VIRTEX4 //`define VIRTEX5