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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [rtl/] [altera_ram/] [altera_ram_syn.v] - Rev 12
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// megafunction wizard: %RAM: 1-PORT% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altsyncram // ============================================================ // File Name: altera_ram.v // Megafunction Name(s): // altsyncram // // Simulation Library Files(s): // altera_mf // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // // 9.0 Build 235 06/17/2009 SP 2 SJ Full Version // ************************************************************ //Copyright (C) 1991-2009 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Altera Program License //Subscription Agreement, Altera MegaCore Function License //Agreement, or other applicable license agreement, including, //without limitation, that your use is for the sole purpose of //programming logic devices manufactured by Altera and sold by //Altera or its authorized distributors. Please refer to the //applicable agreement for further details. //altsyncram CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" DEVICE_FAMILY="Cyclone III" ENABLE_RUNTIME_MOD="NO" INIT_FILE="./bootrom/boot.mif" NUMWORDS_A=16384 OPERATION_MODE="SINGLE_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" POWER_UP_UNINITIALIZED="FALSE" read_during_write_mode_port_a="NEW_DATA_NO_NBE_READ" WIDTH_A=8 WIDTH_BYTEENA_A=1 WIDTHAD_A=14 address_a clock0 data_a q_a wren_a //VERSION_BEGIN 9.0SP2 cbx_altsyncram 2009:05:19:16:53:16:SJ cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_lpm_add_sub 2009:05:07:10:25:28:SJ cbx_lpm_compare 2009:02:03:01:43:16:SJ cbx_lpm_decode 2008:05:19:10:39:27:SJ cbx_lpm_mux 2009:03:31:01:01:28:SJ cbx_mgl 2009:02:26:16:06:21:SJ cbx_stratix 2008:09:18:16:08:35:SJ cbx_stratixii 2008:11:14:16:08:42:SJ cbx_stratixiii 2009:05:12:13:36:56:SJ cbx_util_mgl 2008:11:21:14:58:47:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 //lpm_decode DEVICE_FAMILY="Cyclone III" LPM_DECODES=2 LPM_WIDTH=1 data enable eq //VERSION_BEGIN 9.0SP2 cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_lpm_add_sub 2009:05:07:10:25:28:SJ cbx_lpm_compare 2009:02:03:01:43:16:SJ cbx_lpm_decode 2008:05:19:10:39:27:SJ cbx_mgl 2009:02:26:16:06:21:SJ cbx_stratix 2008:09:18:16:08:35:SJ cbx_stratixii 2008:11:14:16:08:42:SJ VERSION_END //synthesis_resources = lut 1 //synopsys translate_off `timescale 1 ps / 1 ps //synopsys translate_on module altera_ram_decode ( data, enable, eq) /* synthesis synthesis_clearbox=1 */; input [0:0] data; input enable; output [1:0] eq; `ifndef ALTERA_RESERVED_QIS // synopsys translate_off `endif tri0 [0:0] data; tri1 enable; `ifndef ALTERA_RESERVED_QIS // synopsys translate_on `endif wire [1:0] eq_node; assign eq = eq_node, eq_node = {(data & enable), ((~ data) & enable)}; endmodule //altera_ram_decode //lpm_decode DEVICE_FAMILY="Cyclone III" LPM_DECODES=2 LPM_WIDTH=1 data eq //VERSION_BEGIN 9.0SP2 cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_lpm_add_sub 2009:05:07:10:25:28:SJ cbx_lpm_compare 2009:02:03:01:43:16:SJ cbx_lpm_decode 2008:05:19:10:39:27:SJ cbx_mgl 2009:02:26:16:06:21:SJ cbx_stratix 2008:09:18:16:08:35:SJ cbx_stratixii 2008:11:14:16:08:42:SJ VERSION_END //synthesis_resources = lut 1 //synopsys translate_off `timescale 1 ps / 1 ps //synopsys translate_on module altera_ram_decode1 ( data, eq) /* synthesis synthesis_clearbox=1 */; input [0:0] data; output [1:0] eq; `ifndef ALTERA_RESERVED_QIS // synopsys translate_off `endif tri0 [0:0] data; `ifndef ALTERA_RESERVED_QIS // synopsys translate_on `endif wire enable; wire [1:0] eq_node; assign enable = 1'b1, eq = eq_node, eq_node = {(data & enable), ((~ data) & enable)}; endmodule //altera_ram_decode1 //lpm_mux DEVICE_FAMILY="Cyclone III" LPM_SIZE=2 LPM_WIDTH=8 LPM_WIDTHS=1 data result sel //VERSION_BEGIN 9.0SP2 cbx_lpm_mux 2009:03:31:01:01:28:SJ cbx_mgl 2009:02:26:16:06:21:SJ VERSION_END //synthesis_resources = lut 8 //synopsys translate_off `timescale 1 ps / 1 ps //synopsys translate_on module altera_ram_mux ( data, result, sel) /* synthesis synthesis_clearbox=1 */; input [15:0] data; output [7:0] result; input [0:0] sel; `ifndef ALTERA_RESERVED_QIS // synopsys translate_off `endif tri0 [15:0] data; tri0 [0:0] sel; `ifndef ALTERA_RESERVED_QIS // synopsys translate_on `endif wire [7:0] result_node; wire [0:0] sel_node; wire [1:0] w_data130w; wire [1:0] w_data144w; wire [1:0] w_data156w; wire [1:0] w_data168w; wire [1:0] w_data180w; wire [1:0] w_data192w; wire [1:0] w_data204w; wire [1:0] w_data216w; assign result = result_node, result_node = {((sel_node & w_data216w[1]) | ((~ sel_node) & w_data216w[0])), ((sel_node & w_data204w[1]) | ((~ sel_node) & w_data204w[0])), ((sel_node & w_data192w[1]) | ((~ sel_node) & w_data192w[0])), ((sel_node & w_data180w[1]) | ((~ sel_node) & w_data180w[0])), ((sel_node & w_data168w[1]) | ((~ sel_node) & w_data168w[0])), ((sel_node & w_data156w[1]) | ((~ sel_node) & w_data156w[0])), ((sel_node & w_data144w[1]) | ((~ sel_node) & w_data144w[0])), ((sel_node & w_data130w[1]) | ((~ sel_node) & w_data130w[0]))}, sel_node = {sel[0]}, w_data130w = {data[8], data[0]}, w_data144w = {data[9], data[1]}, w_data156w = {data[10], data[2]}, w_data168w = {data[11], data[3]}, w_data180w = {data[12], data[4]}, w_data192w = {data[13], data[5]}, w_data204w = {data[14], data[6]}, w_data216w = {data[15], data[7]}; endmodule //altera_ram_mux //synthesis_resources = lut 10 M9K 16 reg 2 //synopsys translate_off `timescale 1 ps / 1 ps //synopsys translate_on (* ALTERA_ATTRIBUTE = {"OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"} *) module altera_ram_altsyncram ( address_a, clock0, data_a, q_a, wren_a) /* synthesis synthesis_clearbox=1 */; input [13:0] address_a; input clock0; input [7:0] data_a; output [7:0] q_a; input wren_a; `ifndef ALTERA_RESERVED_QIS // synopsys translate_off `endif tri1 clock0; tri1 [7:0] data_a; tri0 wren_a; `ifndef ALTERA_RESERVED_QIS // synopsys translate_on `endif reg [0:0] address_reg_a; reg [0:0] out_address_reg_a; wire [1:0] wire_decode3_eq; wire [1:0] wire_rden_decode_eq; wire [7:0] wire_mux2_result; wire [0:0] wire_ram_block1a_0portadataout; wire [0:0] wire_ram_block1a_1portadataout; wire [0:0] wire_ram_block1a_2portadataout; wire [0:0] wire_ram_block1a_3portadataout; wire [0:0] wire_ram_block1a_4portadataout; wire [0:0] wire_ram_block1a_5portadataout; wire [0:0] wire_ram_block1a_6portadataout; wire [0:0] wire_ram_block1a_7portadataout; wire [0:0] wire_ram_block1a_8portadataout; wire [0:0] wire_ram_block1a_9portadataout; wire [0:0] wire_ram_block1a_10portadataout; wire [0:0] wire_ram_block1a_11portadataout; wire [0:0] wire_ram_block1a_12portadataout; wire [0:0] wire_ram_block1a_13portadataout; wire [0:0] wire_ram_block1a_14portadataout; wire [0:0] wire_ram_block1a_15portadataout; wire [0:0] address_a_sel; wire [13:0] address_a_wire; wire [0:0] rden_decode_addr_sel_a; // synopsys translate_off initial address_reg_a = 0; // synopsys translate_on always @ ( posedge clock0) address_reg_a <= address_a_sel; // synopsys translate_off initial out_address_reg_a = 0; // synopsys translate_on always @ ( posedge clock0) out_address_reg_a <= address_reg_a; altera_ram_decode decode3 ( .data(address_a_wire[13]), .enable(wren_a), .eq(wire_decode3_eq)); altera_ram_decode1 rden_decode ( .data(rden_decode_addr_sel_a), .eq(wire_rden_decode_eq)); altera_ram_mux mux2 ( .data({wire_ram_block1a_15portadataout[0], wire_ram_block1a_14portadataout[0], wire_ram_block1a_13portadataout[0], wire_ram_block1a_12portadataout[0], wire_ram_block1a_11portadataout[0], wire_ram_block1a_10portadataout[0], wire_ram_block1a_9portadataout[0], wire_ram_block1a_8portadataout[0], wire_ram_block1a_7portadataout[0], wire_ram_block1a_6portadataout[0], wire_ram_block1a_5portadataout[0], wire_ram_block1a_4portadataout[0], wire_ram_block1a_3portadataout[0], wire_ram_block1a_2portadataout[0], wire_ram_block1a_1portadataout[0], wire_ram_block1a_0portadataout[0]}), .result(wire_mux2_result), .sel(out_address_reg_a)); cycloneiii_ram_block ram_block1a_0 ( .clk0(clock0), .ena0(wire_rden_decode_eq[0]), .portaaddr({address_a_wire[12:0]}), .portadatain({data_a[0]}), .portadataout(wire_ram_block1a_0portadataout[0:0]), .portare(1'b1), .portawe(wire_decode3_eq[0]), .portbdataout() `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena1(1'b1), .ena2(1'b1), .ena3(1'b1), .portaaddrstall(1'b0), .portabyteenamasks({1{1'b1}}), .portbaddr({1{1'b0}}), .portbaddrstall(1'b0), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}), .portbre(1'b1), .portbwe(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_0.clk0_core_clock_enable = "ena0", ram_block1a_0.clk0_input_clock_enable = "none", ram_block1a_0.clk0_output_clock_enable = "none", ram_block1a_0.connectivity_checking = "OFF", ram_block1a_0.init_file = "./bootrom/boot.mif", ram_block1a_0.init_file_layout = "port_a", ram_block1a_0.logical_ram_name = "ALTSYNCRAM", ram_block1a_0.mem_init0 = 2048'h0000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100000000000000000000000104011111111000000001111111100000060001088000000000000000000000000000000000000000000000000014A6020326E5A94, ram_block1a_0.mem_init1 = 2048'h020820000081F9080017E0076022222222222262022333238F1982B01F2A01F008B3A021200222222226202000226202EF3EC226202EF3EE822620332387070F11F80881D093222226203323170209F20182238222222620201F00280226004000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000A71F228001F228001022000010A20A0A2AA8A02001033333332222222233333332222221022222222222222222222222222220231818100201026, ram_block1a_0.mem_init2 = 2048'h013A321A88641195657832514A80001C5CD40207170CAA80000E2E6A280200E2E1A28000E2E24A54001C5CC8114EB75064A72F85CBA928C9D905A4A8AFF641492A2BFD905A4A8AFF641492A2BFD9050950AFF641696547886413E56C5203231F9FE08C31BC31BC31B431BC30B1B1BE01B1B601BE04313171B60102601313601360136013E013E013A013A013A0132013E0132013E0CB13A0132200082202222620222620233323132017BA6201FBA201B2008201B6010201B6010201B601020000000801090013600820000224000021022222226203322223332317601F17E0079787171E0188F08CF180970188F0811800828FF0A000282201F0B002820000, ram_block1a_0.mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_0.operation_mode = "single_port", ram_block1a_0.port_a_address_width = 13, ram_block1a_0.port_a_byte_enable_mask_width = 1, ram_block1a_0.port_a_byte_size = 1, ram_block1a_0.port_a_data_out_clear = "none", ram_block1a_0.port_a_data_out_clock = "clock0", ram_block1a_0.port_a_data_width = 1, ram_block1a_0.port_a_first_address = 0, ram_block1a_0.port_a_first_bit_number = 0, ram_block1a_0.port_a_last_address = 8191, ram_block1a_0.port_a_logical_ram_depth = 16384, ram_block1a_0.port_a_logical_ram_width = 8, ram_block1a_0.port_a_read_during_write_mode = "new_data_no_nbe_read", ram_block1a_0.power_up_uninitialized = "false", ram_block1a_0.ram_block_type = "AUTO", ram_block1a_0.lpm_type = "cycloneiii_ram_block"; cycloneiii_ram_block ram_block1a_1 ( .clk0(clock0), .ena0(wire_rden_decode_eq[0]), .portaaddr({address_a_wire[12:0]}), .portadatain({data_a[1]}), .portadataout(wire_ram_block1a_1portadataout[0:0]), .portare(1'b1), .portawe(wire_decode3_eq[0]), .portbdataout() `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena1(1'b1), .ena2(1'b1), .ena3(1'b1), .portaaddrstall(1'b0), .portabyteenamasks({1{1'b1}}), .portbaddr({1{1'b0}}), .portbaddrstall(1'b0), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}), .portbre(1'b1), .portbwe(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_1.clk0_core_clock_enable = "ena0", ram_block1a_1.clk0_input_clock_enable = "none", ram_block1a_1.clk0_output_clock_enable = "none", ram_block1a_1.connectivity_checking = "OFF", ram_block1a_1.init_file = "./bootrom/boot.mif", ram_block1a_1.init_file_layout = "port_a", ram_block1a_1.logical_ram_name = "ALTSYNCRAM", ram_block1a_1.mem_init0 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006011111111111111110000000000000000000C0000000000000000000000000000000000000000000000000001AD8010140D3900, ram_block1a_1.mem_init1 = 2048'h802002002081F119300F201F200000000000004001100000070002A2072220F02022B0B0200000000004000000004000EF2EC004000EF2EA8004000000078F2F00F80802C2820000040000000F0202F200822282000004000207000200040020000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002F070000007000000822000000A2020A0AA820A000011111111111111100000000000000000000000000000000000000000000000804080200804, ram_block1a_1.mem_init2 = 2048'h00C4130A40951048123152263C00403A0A32000E82949900001D0549900201D052110021D05181B0003A0A2A2C5E852248195389B214D88045429F012B6150A7C04AD85421F012B615087C04AD85427E01AB615098662FA79511058C9000000F2F20ACF07CF074F07CF07CF870F0F600707E00720CF0F0F0F60002E00F0F600F600F600FE00FE00FE00FE00FE00F600F200F600F20CF07E0070E000822000004000004001000000F6007A222007A2200FE008200F2008A20FA008220F2008A0000282908008007A008A000800800086040000000400111111000000F200707202727176F020088701DF002278008F0160828028F800222282200702222000808, ram_block1a_1.mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_1.operation_mode = "single_port", ram_block1a_1.port_a_address_width = 13, ram_block1a_1.port_a_byte_enable_mask_width = 1, ram_block1a_1.port_a_byte_size = 1, ram_block1a_1.port_a_data_out_clear = "none", ram_block1a_1.port_a_data_out_clock = "clock0", ram_block1a_1.port_a_data_width = 1, ram_block1a_1.port_a_first_address = 0, ram_block1a_1.port_a_first_bit_number = 1, ram_block1a_1.port_a_last_address = 8191, ram_block1a_1.port_a_logical_ram_depth = 16384, ram_block1a_1.port_a_logical_ram_width = 8, ram_block1a_1.port_a_read_during_write_mode = "new_data_no_nbe_read", ram_block1a_1.power_up_uninitialized = "false", ram_block1a_1.ram_block_type = "AUTO", ram_block1a_1.lpm_type = "cycloneiii_ram_block"; cycloneiii_ram_block ram_block1a_2 ( .clk0(clock0), .ena0(wire_rden_decode_eq[0]), .portaaddr({address_a_wire[12:0]}), .portadatain({data_a[2]}), .portadataout(wire_ram_block1a_2portadataout[0:0]), .portare(1'b1), .portawe(wire_decode3_eq[0]), .portbdataout() `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena1(1'b1), .ena2(1'b1), .ena3(1'b1), .portaaddrstall(1'b0), .portabyteenamasks({1{1'b1}}), .portbaddr({1{1'b0}}), .portbaddrstall(1'b0), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}), .portbre(1'b1), .portbwe(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_2.clk0_core_clock_enable = "ena0", ram_block1a_2.clk0_input_clock_enable = "none", ram_block1a_2.clk0_output_clock_enable = "none", ram_block1a_2.connectivity_checking = "OFF", ram_block1a_2.init_file = "./bootrom/boot.mif", ram_block1a_2.init_file_layout = "port_a", ram_block1a_2.logical_ram_name = "ALTSYNCRAM", ram_block1a_2.mem_init0 = 2048'h000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000000000000000000000011008888888888888888888888888888884000110000000000000000000000000000000000000000000000000001CF8000470540E4, ram_block1a_2.mem_init1 = 2048'h0200200201807880011FC007C0191919191199D91191919117B391131F1111700188020181019191199D9113A091D911DE1D991D911DE1DC091D11919197178E31FB3138F890911195119191173121712101109191119591121F333A091D1100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001119191E1F33B121F33B1010319191110010102101010101119191919191919191919119191911119191919191919191919119191911191111113911995, ram_block1a_2.mem_init2 = 2048'h010A77788048D99394C084A14480400590840201642120002002C84A0000002C84A800002C875A4400059091910338409B042D001B897D6D123404A404848D0129012123404A404848D01290121234094A84848D3C4940CBC8DB4989211191161EC09D71F5F17D71FDF17D79F1F1F40171FC017C0DF1F1F17C0191401F1FC017401FC017C01F4017C01F4017C01F4017C01F4017C0DF17C01F3401390801119591191D1191919117C01F910111F9102174028111740189317C0189117C01813301290999291917409813321335393141891911195911919191919117401627C0B63736171C0108F33FF19B3F1108733119B911B7B23300081911F31120128120, ram_block1a_2.mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_2.operation_mode = "single_port", ram_block1a_2.port_a_address_width = 13, ram_block1a_2.port_a_byte_enable_mask_width = 1, ram_block1a_2.port_a_byte_size = 1, ram_block1a_2.port_a_data_out_clear = "none", ram_block1a_2.port_a_data_out_clock = "clock0", ram_block1a_2.port_a_data_width = 1, ram_block1a_2.port_a_first_address = 0, ram_block1a_2.port_a_first_bit_number = 2, ram_block1a_2.port_a_last_address = 8191, ram_block1a_2.port_a_logical_ram_depth = 16384, ram_block1a_2.port_a_logical_ram_width = 8, ram_block1a_2.port_a_read_during_write_mode = "new_data_no_nbe_read", ram_block1a_2.power_up_uninitialized = "false", ram_block1a_2.ram_block_type = "AUTO", ram_block1a_2.lpm_type = "cycloneiii_ram_block"; cycloneiii_ram_block ram_block1a_3 ( .clk0(clock0), .ena0(wire_rden_decode_eq[0]), .portaaddr({address_a_wire[12:0]}), .portadatain({data_a[3]}), .portadataout(wire_ram_block1a_3portadataout[0:0]), .portare(1'b1), .portawe(wire_decode3_eq[0]), .portbdataout() `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena1(1'b1), .ena2(1'b1), .ena3(1'b1), .portaaddrstall(1'b0), .portabyteenamasks({1{1'b1}}), .portbaddr({1{1'b0}}), .portbaddrstall(1'b0), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}), .portbre(1'b1), .portbwe(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_3.clk0_core_clock_enable = "ena0", ram_block1a_3.clk0_input_clock_enable = "none", ram_block1a_3.clk0_output_clock_enable = "none", ram_block1a_3.connectivity_checking = "OFF", ram_block1a_3.init_file = "./bootrom/boot.mif", ram_block1a_3.init_file_layout = "port_a", ram_block1a_3.logical_ram_name = "ALTSYNCRAM", ram_block1a_3.mem_init0 = 2048'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110000000000000000000000000000001111084100000000000000000000000000000000000000000000000000A4B00030670024, ram_block1a_3.mem_init1 = 2048'h91B95395B111E1113116111E918008800884905948008800173313030F1030E55111151111180088490514041110D140DE1D110D140DE1DD110D1488009696B630611193FB118841051488000F1123613181119188410514050F1011110D1011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000400881E0F001150F001110001C84004511111111111111040880088008800880088008008800040C840C840C840C840C840840C84009800000110008CD, ram_block1a_3.mem_init2 = 2048'h01C1032CC4C01158C601007768802020008601080000308010100063080101000030801100012344012000803F1B2270AA027D0053BDD80510061408400401850210010061408400401850210010062810C0040199436ACFC01060E809480016369135E06DE0ED60ED606DE9E060E110606110E91DE0606069101311060E11061106110E910E11061106910E910E91069106110E91DE0611060111499918490D14010D9400880006110F911110F9153069130910E110013061100130E91001105971711151110611109115905921699110088490D94800880088000E110E3691363E1E3E191001711DE0133E100171130139118F951163101830F30155111151, ram_block1a_3.mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_3.operation_mode = "single_port", ram_block1a_3.port_a_address_width = 13, ram_block1a_3.port_a_byte_enable_mask_width = 1, ram_block1a_3.port_a_byte_size = 1, ram_block1a_3.port_a_data_out_clear = "none", ram_block1a_3.port_a_data_out_clock = "clock0", ram_block1a_3.port_a_data_width = 1, ram_block1a_3.port_a_first_address = 0, ram_block1a_3.port_a_first_bit_number = 3, ram_block1a_3.port_a_last_address = 8191, ram_block1a_3.port_a_logical_ram_depth = 16384, ram_block1a_3.port_a_logical_ram_width = 8, ram_block1a_3.port_a_read_during_write_mode = "new_data_no_nbe_read", ram_block1a_3.power_up_uninitialized = "false", ram_block1a_3.ram_block_type = "AUTO", ram_block1a_3.lpm_type = "cycloneiii_ram_block"; cycloneiii_ram_block ram_block1a_4 ( .clk0(clock0), .ena0(wire_rden_decode_eq[0]), .portaaddr({address_a_wire[12:0]}), .portadatain({data_a[4]}), .portadataout(wire_ram_block1a_4portadataout[0:0]), .portare(1'b1), .portawe(wire_decode3_eq[0]), .portbdataout() `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena1(1'b1), .ena2(1'b1), .ena3(1'b1), .portaaddrstall(1'b0), .portabyteenamasks({1{1'b1}}), .portbaddr({1{1'b0}}), .portbaddrstall(1'b0), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}), .portbre(1'b1), .portbwe(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_4.clk0_core_clock_enable = "ena0", ram_block1a_4.clk0_input_clock_enable = "none", ram_block1a_4.clk0_output_clock_enable = "none", ram_block1a_4.connectivity_checking = "OFF", ram_block1a_4.init_file = "./bootrom/boot.mif", ram_block1a_4.init_file_layout = "port_a", ram_block1a_4.logical_ram_name = "ALTSYNCRAM", ram_block1a_4.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000000000000000000000001445000000000000000000000000000000450110C00000000000000000000000000000000000000000000000000020103044086941, ram_block1a_4.mem_init1 = 2048'h21925921112AE22205164556C55159D9D15115D9088800001E1101001E10016771000101095D9D15195510050115D100DF1D115D100DF1D8115D90000016169F11699011D91015195D9000001E1041600111000115195D10051E1000515D140100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000161E400151E40015190055111011911100111111510800008888000088880000888000010D115599DD115599DD11559DD11550981018101011095, ram_block1a_4.mem_init2 = 2048'h004444123E950A8000354280063FB03A0831FF8E82108B1FF81D0410B1FF81D0468B1FF9D0449031FFBA082A04D00F1E11190CBCA58001A24540FB1D0B01503EC742C0540FB1D0B01503EC742C0540F63B2B015001840C0015080431B900001617451D61ED61EDE1EDE16DE1E161645161E451E45D6161616C5101C51616451E451EC51E451E4516C5164516C516451E451EC51E45D616C5161C51590015195510015D9088000016C51E911011E91501E4501921E45119016C51190164511900795951915191164511900591550951C1D9D151955100008888000016C5160E459616361E145182673FE1891E9102E731189101AE951002091021E1023111A152, ram_block1a_4.mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_4.operation_mode = "single_port", ram_block1a_4.port_a_address_width = 13, ram_block1a_4.port_a_byte_enable_mask_width = 1, ram_block1a_4.port_a_byte_size = 1, ram_block1a_4.port_a_data_out_clear = "none", ram_block1a_4.port_a_data_out_clock = "clock0", ram_block1a_4.port_a_data_width = 1, ram_block1a_4.port_a_first_address = 0, ram_block1a_4.port_a_first_bit_number = 4, ram_block1a_4.port_a_last_address = 8191, ram_block1a_4.port_a_logical_ram_depth = 16384, ram_block1a_4.port_a_logical_ram_width = 8, ram_block1a_4.port_a_read_during_write_mode = "new_data_no_nbe_read", ram_block1a_4.power_up_uninitialized = "false", ram_block1a_4.ram_block_type = "AUTO", ram_block1a_4.lpm_type = "cycloneiii_ram_block"; cycloneiii_ram_block ram_block1a_5 ( .clk0(clock0), .ena0(wire_rden_decode_eq[0]), .portaaddr({address_a_wire[12:0]}), .portadatain({data_a[5]}), .portadataout(wire_ram_block1a_5portadataout[0:0]), .portare(1'b1), .portawe(wire_decode3_eq[0]), .portbdataout() `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena1(1'b1), .ena2(1'b1), .ena3(1'b1), .portaaddrstall(1'b0), .portabyteenamasks({1{1'b1}}), .portbaddr({1{1'b0}}), .portbaddrstall(1'b0), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}), .portbre(1'b1), .portbwe(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_5.clk0_core_clock_enable = "ena0", ram_block1a_5.clk0_input_clock_enable = "none", ram_block1a_5.clk0_output_clock_enable = "none", ram_block1a_5.connectivity_checking = "OFF", ram_block1a_5.init_file = "./bootrom/boot.mif", ram_block1a_5.init_file_layout = "port_a", ram_block1a_5.logical_ram_name = "ALTSYNCRAM", ram_block1a_5.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000014313131313131313131313131313131F61000030000000000000000000000000000000000000000000000000FDFEFEFEE90EC01, ram_block1a_5.mem_init1 = 2048'h143301343211E111120E360E3688C40044008062000000022E1003320E1320600211141092200440000E20001000E200EE3EA00E200EE3EB200E20000226261E306AA011C10140000E2000020E1030E23001210340000E20000E3903400E001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008A8A2E0E5B2840E5B2840012CCCC00440404124040406008A8A820202020A8A8A8A8020202000CCC880044440088CCCC8804444001A20808001130006, ram_block1a_5.mem_init2 = 2048'h007FFFFC3F823F87E1F9E9E007FFBFFFBD01FFFFEF7A0C7FFFFFDE80C7FFFFFDE80C7FFFFDEFF03FFFFFBD0404FF7E1FFF7E0C7FDD807FFFE081FF7FFFF8207FDFFFFE081FF7FFFF8207FDFFFFE081FEFFFFF8207BD00FC3823FF3FFE200020E0E36BEE06EE06EE06EE0EEEA60E0EB60E0E360E36E6060606B6003B60E06B606B606B6063606B60EB60E360E360E360E360EB60E36E606360643600A1320000E20000E200000020EB60E926020E92030E3630920EB6001206B600920636001220A0208A808280EB6801220220A2002B0A0440000EA08880000000206360E16363E060E06036001630CE0030620816300003A83BE902251303320E11244243003, ram_block1a_5.mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_5.operation_mode = "single_port", ram_block1a_5.port_a_address_width = 13, ram_block1a_5.port_a_byte_enable_mask_width = 1, ram_block1a_5.port_a_byte_size = 1, ram_block1a_5.port_a_data_out_clear = "none", ram_block1a_5.port_a_data_out_clock = "clock0", ram_block1a_5.port_a_data_width = 1, ram_block1a_5.port_a_first_address = 0, ram_block1a_5.port_a_first_bit_number = 5, ram_block1a_5.port_a_last_address = 8191, ram_block1a_5.port_a_logical_ram_depth = 16384, ram_block1a_5.port_a_logical_ram_width = 8, ram_block1a_5.port_a_read_during_write_mode = "new_data_no_nbe_read", ram_block1a_5.power_up_uninitialized = "false", ram_block1a_5.ram_block_type = "AUTO", ram_block1a_5.lpm_type = "cycloneiii_ram_block"; cycloneiii_ram_block ram_block1a_6 ( .clk0(clock0), .ena0(wire_rden_decode_eq[0]), .portaaddr({address_a_wire[12:0]}), .portadatain({data_a[6]}), .portadataout(wire_ram_block1a_6portadataout[0:0]), .portare(1'b1), .portawe(wire_decode3_eq[0]), .portbdataout() `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena1(1'b1), .ena2(1'b1), .ena3(1'b1), .portaaddrstall(1'b0), .portabyteenamasks({1{1'b1}}), .portbaddr({1{1'b0}}), .portbaddrstall(1'b0), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}), .portbre(1'b1), .portbwe(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_6.clk0_core_clock_enable = "ena0", ram_block1a_6.clk0_input_clock_enable = "none", ram_block1a_6.clk0_output_clock_enable = "none", ram_block1a_6.connectivity_checking = "OFF", ram_block1a_6.init_file = "./bootrom/boot.mif", ram_block1a_6.init_file_layout = "port_a", ram_block1a_6.logical_ram_name = "ALTSYNCRAM", ram_block1a_6.mem_init0 = 2048'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001263311331133113311331133113311338400001200000000000000000000000000000000000000000000000001EFF010776F13F1, ram_block1a_6.mem_init1 = 2048'h01A01801A002E022062EA64E26551111555521C0520202202E2000220E0220E11222012000611555521C05210421C052EE2EA21C052EE2E2221C0502202E2E8E20E22022C80255521C0502200E0072E22200200055521C05210E0000221C2122000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000500222E0E180A10E10020001211110511010100101018205A88AA88AA88AA00220022022002205DDDDDDD99999911555555511111108000000000A0054, ram_block1a_6.mem_init2 = 2048'h000F777E047DDBC3F0FCF6F01800601FDEF00107F7BD8380100FEF78380100FEF7838010FEF7F8C0011FDEFB870FBF007FBF0381FE003DEFDF700FBDEFF7DC03EF7BFDF700FBDEFF7DC03EF7BFDF701F7BEFF7DC3DEC07E07DDBEDFDF052202E2EA60EE0EEE0EEE0EEE0EEE260E06A60606A606A6E60E0E0E2600026060E260E260EA60EA60E260EA60EA60E260E260EA60EA60EA6EE06A6061A601A0065521C05221C0502022006260E223020E22120626208206A600820E2600020E26000221A1A182A1A280EA6808221A2162010E021555521C052020202022006A60E26A60E260E262A6000E60CE00026A000E6020002002EA10212000220E00211012010, ram_block1a_6.mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_6.operation_mode = "single_port", ram_block1a_6.port_a_address_width = 13, ram_block1a_6.port_a_byte_enable_mask_width = 1, ram_block1a_6.port_a_byte_size = 1, ram_block1a_6.port_a_data_out_clear = "none", ram_block1a_6.port_a_data_out_clock = "clock0", ram_block1a_6.port_a_data_width = 1, ram_block1a_6.port_a_first_address = 0, ram_block1a_6.port_a_first_bit_number = 6, ram_block1a_6.port_a_last_address = 8191, ram_block1a_6.port_a_logical_ram_depth = 16384, ram_block1a_6.port_a_logical_ram_width = 8, ram_block1a_6.port_a_read_during_write_mode = "new_data_no_nbe_read", ram_block1a_6.power_up_uninitialized = "false", ram_block1a_6.ram_block_type = "AUTO", ram_block1a_6.lpm_type = "cycloneiii_ram_block"; cycloneiii_ram_block ram_block1a_7 ( .clk0(clock0), .ena0(wire_rden_decode_eq[0]), .portaaddr({address_a_wire[12:0]}), .portadatain({data_a[7]}), .portadataout(wire_ram_block1a_7portadataout[0:0]), .portare(1'b1), .portawe(wire_decode3_eq[0]), .portbdataout() `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena1(1'b1), .ena2(1'b1), .ena3(1'b1), .portaaddrstall(1'b0), .portabyteenamasks({1{1'b1}}), .portbaddr({1{1'b0}}), .portbaddrstall(1'b0), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}), .portbre(1'b1), .portbwe(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_7.clk0_core_clock_enable = "ena0", ram_block1a_7.clk0_input_clock_enable = "none", ram_block1a_7.clk0_output_clock_enable = "none", ram_block1a_7.connectivity_checking = "OFF", ram_block1a_7.init_file = "./bootrom/boot.mif", ram_block1a_7.init_file_layout = "port_a", ram_block1a_7.logical_ram_name = "ALTSYNCRAM", ram_block1a_7.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000014333311113333111133331111333311141000110000000000000000000000000000000000000000000000000000000000000001, ram_block1a_7.mem_init1 = 2048'h31131331133161133116140614555555111111D1011331111E1301110E1110E11131111333055111111D10113211D101DE1D911D101DE1D1011D1031111E1E3E10E11011F33111111D1031110E1311E11101130111111D10110E1333211D1010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000033331E0E133310E133320013111100113131B313131B0003331111333311113333111333311005555555555555551111111111111011000800131001D, ram_block1a_7.mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101111E1E141D606D606D606D606D6160606940606940614DE0E060694001940E069406940614061406140694069406940694061406140614DE0E140E1143193301111D10111D101331110E140E113310E11110E1410110E9400110E9400110E94001111111111311130E14301111111913131305111111D101133113311106140E36141E363E16314003E13F6001361003E1310011011E913133301110E13111311313, ram_block1a_7.mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_7.operation_mode = "single_port", ram_block1a_7.port_a_address_width = 13, ram_block1a_7.port_a_byte_enable_mask_width = 1, ram_block1a_7.port_a_byte_size = 1, ram_block1a_7.port_a_data_out_clear = "none", ram_block1a_7.port_a_data_out_clock = "clock0", ram_block1a_7.port_a_data_width = 1, ram_block1a_7.port_a_first_address = 0, ram_block1a_7.port_a_first_bit_number = 7, ram_block1a_7.port_a_last_address = 8191, ram_block1a_7.port_a_logical_ram_depth = 16384, ram_block1a_7.port_a_logical_ram_width = 8, ram_block1a_7.port_a_read_during_write_mode = "new_data_no_nbe_read", ram_block1a_7.power_up_uninitialized = "false", ram_block1a_7.ram_block_type = "AUTO", ram_block1a_7.lpm_type = "cycloneiii_ram_block"; cycloneiii_ram_block ram_block1a_8 ( .clk0(clock0), .ena0(wire_rden_decode_eq[1]), .portaaddr({address_a_wire[12:0]}), .portadatain({data_a[0]}), .portadataout(wire_ram_block1a_8portadataout[0:0]), .portare(1'b1), .portawe(wire_decode3_eq[1]), .portbdataout() `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena1(1'b1), .ena2(1'b1), .ena3(1'b1), .portaaddrstall(1'b0), .portabyteenamasks({1{1'b1}}), .portbaddr({1{1'b0}}), .portbaddrstall(1'b0), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}), .portbre(1'b1), .portbwe(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_8.clk0_core_clock_enable = "ena0", ram_block1a_8.clk0_input_clock_enable = "none", ram_block1a_8.clk0_output_clock_enable = "none", ram_block1a_8.connectivity_checking = "OFF", ram_block1a_8.init_file = "./bootrom/boot.mif", ram_block1a_8.init_file_layout = "port_a", ram_block1a_8.logical_ram_name = "ALTSYNCRAM", ram_block1a_8.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_8.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_8.mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_8.mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_8.operation_mode = "single_port", ram_block1a_8.port_a_address_width = 13, ram_block1a_8.port_a_byte_enable_mask_width = 1, ram_block1a_8.port_a_byte_size = 1, ram_block1a_8.port_a_data_out_clear = "none", ram_block1a_8.port_a_data_out_clock = "clock0", ram_block1a_8.port_a_data_width = 1, ram_block1a_8.port_a_first_address = 8192, ram_block1a_8.port_a_first_bit_number = 0, ram_block1a_8.port_a_last_address = 16383, ram_block1a_8.port_a_logical_ram_depth = 16384, ram_block1a_8.port_a_logical_ram_width = 8, ram_block1a_8.port_a_read_during_write_mode = "new_data_no_nbe_read", ram_block1a_8.power_up_uninitialized = "false", ram_block1a_8.ram_block_type = "AUTO", ram_block1a_8.lpm_type = "cycloneiii_ram_block"; cycloneiii_ram_block ram_block1a_9 ( .clk0(clock0), .ena0(wire_rden_decode_eq[1]), .portaaddr({address_a_wire[12:0]}), .portadatain({data_a[1]}), .portadataout(wire_ram_block1a_9portadataout[0:0]), .portare(1'b1), .portawe(wire_decode3_eq[1]), .portbdataout() `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena1(1'b1), .ena2(1'b1), .ena3(1'b1), .portaaddrstall(1'b0), .portabyteenamasks({1{1'b1}}), .portbaddr({1{1'b0}}), .portbaddrstall(1'b0), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}), .portbre(1'b1), .portbwe(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_9.clk0_core_clock_enable = "ena0", ram_block1a_9.clk0_input_clock_enable = "none", ram_block1a_9.clk0_output_clock_enable = "none", ram_block1a_9.connectivity_checking = "OFF", ram_block1a_9.init_file = "./bootrom/boot.mif", ram_block1a_9.init_file_layout = "port_a", ram_block1a_9.logical_ram_name = "ALTSYNCRAM", ram_block1a_9.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_9.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_9.mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_9.mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_9.operation_mode = "single_port", ram_block1a_9.port_a_address_width = 13, ram_block1a_9.port_a_byte_enable_mask_width = 1, ram_block1a_9.port_a_byte_size = 1, ram_block1a_9.port_a_data_out_clear = "none", ram_block1a_9.port_a_data_out_clock = "clock0", ram_block1a_9.port_a_data_width = 1, ram_block1a_9.port_a_first_address = 8192, ram_block1a_9.port_a_first_bit_number = 1, ram_block1a_9.port_a_last_address = 16383, ram_block1a_9.port_a_logical_ram_depth = 16384, ram_block1a_9.port_a_logical_ram_width = 8, ram_block1a_9.port_a_read_during_write_mode = "new_data_no_nbe_read", ram_block1a_9.power_up_uninitialized = "false", ram_block1a_9.ram_block_type = "AUTO", ram_block1a_9.lpm_type = "cycloneiii_ram_block"; cycloneiii_ram_block ram_block1a_10 ( .clk0(clock0), .ena0(wire_rden_decode_eq[1]), .portaaddr({address_a_wire[12:0]}), .portadatain({data_a[2]}), .portadataout(wire_ram_block1a_10portadataout[0:0]), .portare(1'b1), .portawe(wire_decode3_eq[1]), .portbdataout() `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena1(1'b1), .ena2(1'b1), .ena3(1'b1), .portaaddrstall(1'b0), .portabyteenamasks({1{1'b1}}), .portbaddr({1{1'b0}}), .portbaddrstall(1'b0), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}), .portbre(1'b1), .portbwe(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_10.clk0_core_clock_enable = "ena0", ram_block1a_10.clk0_input_clock_enable = "none", ram_block1a_10.clk0_output_clock_enable = "none", ram_block1a_10.connectivity_checking = "OFF", ram_block1a_10.init_file = "./bootrom/boot.mif", ram_block1a_10.init_file_layout = "port_a", ram_block1a_10.logical_ram_name = "ALTSYNCRAM", ram_block1a_10.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_10.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_10.mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_10.mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_10.operation_mode = "single_port", ram_block1a_10.port_a_address_width = 13, ram_block1a_10.port_a_byte_enable_mask_width = 1, ram_block1a_10.port_a_byte_size = 1, ram_block1a_10.port_a_data_out_clear = "none", ram_block1a_10.port_a_data_out_clock = "clock0", ram_block1a_10.port_a_data_width = 1, ram_block1a_10.port_a_first_address = 8192, ram_block1a_10.port_a_first_bit_number = 2, ram_block1a_10.port_a_last_address = 16383, ram_block1a_10.port_a_logical_ram_depth = 16384, ram_block1a_10.port_a_logical_ram_width = 8, ram_block1a_10.port_a_read_during_write_mode = "new_data_no_nbe_read", ram_block1a_10.power_up_uninitialized = "false", ram_block1a_10.ram_block_type = "AUTO", ram_block1a_10.lpm_type = "cycloneiii_ram_block"; cycloneiii_ram_block ram_block1a_11 ( .clk0(clock0), .ena0(wire_rden_decode_eq[1]), .portaaddr({address_a_wire[12:0]}), .portadatain({data_a[3]}), .portadataout(wire_ram_block1a_11portadataout[0:0]), .portare(1'b1), .portawe(wire_decode3_eq[1]), .portbdataout() `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena1(1'b1), .ena2(1'b1), .ena3(1'b1), .portaaddrstall(1'b0), .portabyteenamasks({1{1'b1}}), .portbaddr({1{1'b0}}), .portbaddrstall(1'b0), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}), .portbre(1'b1), .portbwe(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_11.clk0_core_clock_enable = "ena0", ram_block1a_11.clk0_input_clock_enable = "none", ram_block1a_11.clk0_output_clock_enable = "none", ram_block1a_11.connectivity_checking = "OFF", ram_block1a_11.init_file = "./bootrom/boot.mif", ram_block1a_11.init_file_layout = "port_a", ram_block1a_11.logical_ram_name = "ALTSYNCRAM", ram_block1a_11.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_11.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_11.mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_11.mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_11.operation_mode = "single_port", ram_block1a_11.port_a_address_width = 13, ram_block1a_11.port_a_byte_enable_mask_width = 1, ram_block1a_11.port_a_byte_size = 1, ram_block1a_11.port_a_data_out_clear = "none", ram_block1a_11.port_a_data_out_clock = "clock0", ram_block1a_11.port_a_data_width = 1, ram_block1a_11.port_a_first_address = 8192, ram_block1a_11.port_a_first_bit_number = 3, ram_block1a_11.port_a_last_address = 16383, ram_block1a_11.port_a_logical_ram_depth = 16384, ram_block1a_11.port_a_logical_ram_width = 8, ram_block1a_11.port_a_read_during_write_mode = "new_data_no_nbe_read", ram_block1a_11.power_up_uninitialized = "false", ram_block1a_11.ram_block_type = "AUTO", ram_block1a_11.lpm_type = "cycloneiii_ram_block"; cycloneiii_ram_block ram_block1a_12 ( .clk0(clock0), .ena0(wire_rden_decode_eq[1]), .portaaddr({address_a_wire[12:0]}), .portadatain({data_a[4]}), .portadataout(wire_ram_block1a_12portadataout[0:0]), .portare(1'b1), .portawe(wire_decode3_eq[1]), .portbdataout() `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena1(1'b1), .ena2(1'b1), .ena3(1'b1), .portaaddrstall(1'b0), .portabyteenamasks({1{1'b1}}), .portbaddr({1{1'b0}}), .portbaddrstall(1'b0), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}), .portbre(1'b1), .portbwe(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_12.clk0_core_clock_enable = "ena0", ram_block1a_12.clk0_input_clock_enable = "none", ram_block1a_12.clk0_output_clock_enable = "none", ram_block1a_12.connectivity_checking = "OFF", ram_block1a_12.init_file = "./bootrom/boot.mif", ram_block1a_12.init_file_layout = "port_a", ram_block1a_12.logical_ram_name = "ALTSYNCRAM", ram_block1a_12.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_12.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_12.mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_12.mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_12.operation_mode = "single_port", ram_block1a_12.port_a_address_width = 13, ram_block1a_12.port_a_byte_enable_mask_width = 1, ram_block1a_12.port_a_byte_size = 1, ram_block1a_12.port_a_data_out_clear = "none", ram_block1a_12.port_a_data_out_clock = "clock0", ram_block1a_12.port_a_data_width = 1, ram_block1a_12.port_a_first_address = 8192, ram_block1a_12.port_a_first_bit_number = 4, ram_block1a_12.port_a_last_address = 16383, ram_block1a_12.port_a_logical_ram_depth = 16384, ram_block1a_12.port_a_logical_ram_width = 8, ram_block1a_12.port_a_read_during_write_mode = "new_data_no_nbe_read", ram_block1a_12.power_up_uninitialized = "false", ram_block1a_12.ram_block_type = "AUTO", ram_block1a_12.lpm_type = "cycloneiii_ram_block"; cycloneiii_ram_block ram_block1a_13 ( .clk0(clock0), .ena0(wire_rden_decode_eq[1]), .portaaddr({address_a_wire[12:0]}), .portadatain({data_a[5]}), .portadataout(wire_ram_block1a_13portadataout[0:0]), .portare(1'b1), .portawe(wire_decode3_eq[1]), .portbdataout() `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena1(1'b1), .ena2(1'b1), .ena3(1'b1), .portaaddrstall(1'b0), .portabyteenamasks({1{1'b1}}), .portbaddr({1{1'b0}}), .portbaddrstall(1'b0), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}), .portbre(1'b1), .portbwe(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_13.clk0_core_clock_enable = "ena0", ram_block1a_13.clk0_input_clock_enable = "none", ram_block1a_13.clk0_output_clock_enable = "none", ram_block1a_13.connectivity_checking = "OFF", ram_block1a_13.init_file = "./bootrom/boot.mif", ram_block1a_13.init_file_layout = "port_a", ram_block1a_13.logical_ram_name = "ALTSYNCRAM", ram_block1a_13.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_13.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_13.mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_13.mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_13.operation_mode = "single_port", ram_block1a_13.port_a_address_width = 13, ram_block1a_13.port_a_byte_enable_mask_width = 1, ram_block1a_13.port_a_byte_size = 1, ram_block1a_13.port_a_data_out_clear = "none", ram_block1a_13.port_a_data_out_clock = "clock0", ram_block1a_13.port_a_data_width = 1, ram_block1a_13.port_a_first_address = 8192, ram_block1a_13.port_a_first_bit_number = 5, ram_block1a_13.port_a_last_address = 16383, ram_block1a_13.port_a_logical_ram_depth = 16384, ram_block1a_13.port_a_logical_ram_width = 8, ram_block1a_13.port_a_read_during_write_mode = "new_data_no_nbe_read", ram_block1a_13.power_up_uninitialized = "false", ram_block1a_13.ram_block_type = "AUTO", ram_block1a_13.lpm_type = "cycloneiii_ram_block"; cycloneiii_ram_block ram_block1a_14 ( .clk0(clock0), .ena0(wire_rden_decode_eq[1]), .portaaddr({address_a_wire[12:0]}), .portadatain({data_a[6]}), .portadataout(wire_ram_block1a_14portadataout[0:0]), .portare(1'b1), .portawe(wire_decode3_eq[1]), .portbdataout() `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena1(1'b1), .ena2(1'b1), .ena3(1'b1), .portaaddrstall(1'b0), .portabyteenamasks({1{1'b1}}), .portbaddr({1{1'b0}}), .portbaddrstall(1'b0), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}), .portbre(1'b1), .portbwe(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_14.clk0_core_clock_enable = "ena0", ram_block1a_14.clk0_input_clock_enable = "none", ram_block1a_14.clk0_output_clock_enable = "none", ram_block1a_14.connectivity_checking = "OFF", ram_block1a_14.init_file = "./bootrom/boot.mif", ram_block1a_14.init_file_layout = "port_a", ram_block1a_14.logical_ram_name = "ALTSYNCRAM", ram_block1a_14.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_14.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_14.mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_14.mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_14.operation_mode = "single_port", ram_block1a_14.port_a_address_width = 13, ram_block1a_14.port_a_byte_enable_mask_width = 1, ram_block1a_14.port_a_byte_size = 1, ram_block1a_14.port_a_data_out_clear = "none", ram_block1a_14.port_a_data_out_clock = "clock0", ram_block1a_14.port_a_data_width = 1, ram_block1a_14.port_a_first_address = 8192, ram_block1a_14.port_a_first_bit_number = 6, ram_block1a_14.port_a_last_address = 16383, ram_block1a_14.port_a_logical_ram_depth = 16384, ram_block1a_14.port_a_logical_ram_width = 8, ram_block1a_14.port_a_read_during_write_mode = "new_data_no_nbe_read", ram_block1a_14.power_up_uninitialized = "false", ram_block1a_14.ram_block_type = "AUTO", ram_block1a_14.lpm_type = "cycloneiii_ram_block"; cycloneiii_ram_block ram_block1a_15 ( .clk0(clock0), .ena0(wire_rden_decode_eq[1]), .portaaddr({address_a_wire[12:0]}), .portadatain({data_a[7]}), .portadataout(wire_ram_block1a_15portadataout[0:0]), .portare(1'b1), .portawe(wire_decode3_eq[1]), .portbdataout() `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .clk1(1'b0), .clr0(1'b0), .clr1(1'b0), .ena1(1'b1), .ena2(1'b1), .ena3(1'b1), .portaaddrstall(1'b0), .portabyteenamasks({1{1'b1}}), .portbaddr({1{1'b0}}), .portbaddrstall(1'b0), .portbbyteenamasks({1{1'b1}}), .portbdatain({1{1'b0}}), .portbre(1'b1), .portbwe(1'b0) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devclrn(1'b1), .devpor(1'b1) // synopsys translate_on ); defparam ram_block1a_15.clk0_core_clock_enable = "ena0", ram_block1a_15.clk0_input_clock_enable = "none", ram_block1a_15.clk0_output_clock_enable = "none", ram_block1a_15.connectivity_checking = "OFF", ram_block1a_15.init_file = "./bootrom/boot.mif", ram_block1a_15.init_file_layout = "port_a", ram_block1a_15.logical_ram_name = "ALTSYNCRAM", ram_block1a_15.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_15.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_15.mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_15.mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, ram_block1a_15.operation_mode = "single_port", ram_block1a_15.port_a_address_width = 13, ram_block1a_15.port_a_byte_enable_mask_width = 1, ram_block1a_15.port_a_byte_size = 1, ram_block1a_15.port_a_data_out_clear = "none", ram_block1a_15.port_a_data_out_clock = "clock0", ram_block1a_15.port_a_data_width = 1, ram_block1a_15.port_a_first_address = 8192, ram_block1a_15.port_a_first_bit_number = 7, ram_block1a_15.port_a_last_address = 16383, ram_block1a_15.port_a_logical_ram_depth = 16384, ram_block1a_15.port_a_logical_ram_width = 8, ram_block1a_15.port_a_read_during_write_mode = "new_data_no_nbe_read", ram_block1a_15.power_up_uninitialized = "false", ram_block1a_15.ram_block_type = "AUTO", ram_block1a_15.lpm_type = "cycloneiii_ram_block"; assign address_a_sel = address_a[13], address_a_wire = address_a, q_a = wire_mux2_result, rden_decode_addr_sel_a = address_a_wire[13]; initial/*synthesis enable_verilog_initial_construct*/ begin $display("Warning: Memory initialization file ./bootrom/boot.mif is not of the dimensions 16384 X 8, the resulting memory design may not produce consistent simulation results."); end endmodule //altera_ram_altsyncram //VALID FILE // synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on module altera_ram ( address, clock, data, wren, q)/* synthesis synthesis_clearbox = 1 */; input [13:0] address; input clock; input [7:0] data; input wren; output [7:0] q; `ifndef ALTERA_RESERVED_QIS // synopsys translate_off `endif tri1 clock; `ifndef ALTERA_RESERVED_QIS // synopsys translate_on `endif wire [7:0] sub_wire0; wire [7:0] q = sub_wire0[7:0]; altera_ram_altsyncram altera_ram_altsyncram_component ( .wren_a (wren), .clock0 (clock), .address_a (address), .data_a (data), .q_a (sub_wire0)); endmodule // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" // Retrieval info: PRIVATE: AclrByte NUMERIC "0" // Retrieval info: PRIVATE: AclrData NUMERIC "0" // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" // Retrieval info: PRIVATE: Clken NUMERIC "0" // Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "1" // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" // Retrieval info: PRIVATE: MIFfilename STRING "./bootrom/boot.mif" // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16384" // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" // Retrieval info: PRIVATE: RegAddr NUMERIC "1" // Retrieval info: PRIVATE: RegData NUMERIC "1" // Retrieval info: PRIVATE: RegOutput NUMERIC "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1" // Retrieval info: PRIVATE: SingleClock NUMERIC "1" // Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" // Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" // Retrieval info: PRIVATE: WidthAddr NUMERIC "14" // Retrieval info: PRIVATE: WidthData NUMERIC "8" // Retrieval info: PRIVATE: rden NUMERIC "0" // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: INIT_FILE STRING "./bootrom/boot.mif" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384" // Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14" // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" // Retrieval info: USED_PORT: address 0 0 14 0 INPUT NODEFVAL address[13..0] // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock // Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0] // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0] // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren // Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0 // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 // Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: GEN_FILE: TYPE_NORMAL altera_ram.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL altera_ram.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL altera_ram.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL altera_ram.bsf TRUE FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL altera_ram_inst.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL altera_ram_bb.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL altera_ram_waveforms.html TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL altera_ram_wave*.jpg FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL altera_ram_syn.v TRUE // Retrieval info: LIB_FILE: altera_mf