Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

../../bench/CPUboard_tb.v

../../rtl/spi/rtl/verilog/spi_defines.v
../../rtl/spi/rtl/verilog/spi_shift.v
../../rtl/spi/rtl/verilog/spi_clgen.v
../../rtl/spi/rtl/verilog/spi_top.v
../../rtl/spi/rtl/verilog/timescale.v

../../rtl/wb_conmax/rtl/verilog/wb_conmax_master_if.v
../../rtl/wb_conmax/rtl/verilog/wb_conmax_defines.v
../../rtl/wb_conmax/rtl/verilog/wb_conmax_arb.v
../../rtl/wb_conmax/rtl/verilog/wb_conmax_pri_enc.v
../../rtl/wb_conmax/rtl/verilog/wb_conmax_top.v
../../rtl/wb_conmax/rtl/verilog/wb_conmax_msel.v
../../rtl/wb_conmax/rtl/verilog/wb_conmax_slave_if.v
../../rtl/wb_conmax/rtl/verilog/wb_conmax_rf.v
../../rtl/wb_conmax/rtl/verilog/wb_conmax_pri_dec.v

../../rtl/mem_if/rtl/verilog/mc_wb_if.v
../../rtl/mem_if/rtl/verilog/mc_defines.v
../../rtl/mem_if/rtl/verilog/mc_top.v
../../rtl/mem_if/rtl/verilog/mc_cs_rf.v
../../rtl/mem_if/rtl/verilog/mc_dp.v
../../rtl/mem_if/rtl/verilog/mc_incn_r.v
../../rtl/mem_if/rtl/verilog/mc_timing.v
../../rtl/mem_if/rtl/verilog/mc_adr_sel.v
../../rtl/mem_if/rtl/verilog/mc_mem_if.v
../../rtl/mem_if/rtl/verilog/mc_obct.v
../../rtl/mem_if/rtl/verilog/mc_obct_top.v
../../rtl/mem_if/rtl/verilog/mc_refresh.v
../../rtl/mem_if/rtl/verilog/mc_rf.v
../../rtl/mem_if/rtl/verilog/mc_rd_fifo.v

../../rtl/or1k_sco_top.v

../../rtl/dbg_interface/rtl/verilog/dbg_defines.v
../../rtl/dbg_interface/rtl/verilog/dbg_wb_defines.v
../../rtl/dbg_interface/rtl/verilog/dbg_crc32_d1.v
../../rtl/dbg_interface/rtl/verilog/dbg_top.v
../../rtl/dbg_interface/rtl/verilog/dbg_register.v
../../rtl/dbg_interface/rtl/verilog/dbg_cpu.v
../../rtl/dbg_interface/rtl/verilog/dbg_cpu_defines.v
../../rtl/dbg_interface/rtl/verilog/dbg_cpu_registers.v
../../rtl/dbg_interface/rtl/verilog/dbg_wb.v

../../rtl/rom_wb/rom_wb.v

../../rtl/uart16550/rtl/verilog/uart_top.v
../../rtl/uart16550/rtl/verilog/uart_wb.v
../../rtl/uart16550/rtl/verilog/uart_regs.v
../../rtl/uart16550/rtl/verilog/raminfr.v
../../rtl/uart16550/rtl/verilog/uart_defines.v
../../rtl/uart16550/rtl/verilog/timescale.v
../../rtl/uart16550/rtl/verilog/uart_rfifo.v
../../rtl/uart16550/rtl/verilog/uart_debug_if.v
../../rtl/uart16550/rtl/verilog/uart_tfifo.v
../../rtl/uart16550/rtl/verilog/uart_receiver.v
../../rtl/uart16550/rtl/verilog/uart_sync_flops.v
../../rtl/uart16550/rtl/verilog/uart_transmitter.v

../../rtl/or1200/rtl/verilog/or1200_reg2mem.v
../../rtl/or1200/rtl/verilog/or1200_dpram_32x32.v
../../rtl/or1200/rtl/verilog/or1200_wb_biu.v
../../rtl/or1200/rtl/verilog/or1200_pm.v
../../rtl/or1200/rtl/verilog/or1200_tpram_32x32.v
../../rtl/or1200/rtl/verilog/or1200_gmultp2_32x32.v
../../rtl/or1200/rtl/verilog/or1200_lsu.v
../../rtl/or1200/rtl/verilog/or1200_mem2reg.v
../../rtl/or1200/rtl/verilog/or1200_freeze.v
../../rtl/or1200/rtl/verilog/or1200_cfgr.v
../../rtl/or1200/rtl/verilog/or1200_defines.v
../../rtl/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
../../rtl/or1200/rtl/verilog/or1200_except.v
../../rtl/or1200/rtl/verilog/or1200_pic.v
../../rtl/or1200/rtl/verilog/or1200_dc_tag.v
../../rtl/or1200/rtl/verilog/or1200_rfram_generic.v
../../rtl/or1200/rtl/verilog/or1200_sb_fifo.v
../../rtl/or1200/rtl/verilog/or1200_dc_ram.v
../../rtl/or1200/rtl/verilog/timescale.v
../../rtl/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
../../rtl/or1200/rtl/verilog/or1200_dpram_256x32.v
../../rtl/or1200/rtl/verilog/or1200_cpu.v
../../rtl/or1200/rtl/verilog/or1200_ic_ram.v
../../rtl/or1200/rtl/verilog/or1200_dc_fsm.v
../../rtl/or1200/rtl/verilog/or1200_spram_32x24.v
../../rtl/or1200/rtl/verilog/or1200_mult_mac.v
../../rtl/or1200/rtl/verilog/or1200_spram_256x21.v
../../rtl/or1200/rtl/verilog/or1200_genpc.v
../../rtl/or1200/rtl/verilog/or1200_alu.v
../../rtl/or1200/rtl/verilog/or1200_dmmu_top.v
../../rtl/or1200/rtl/verilog/or1200_ic_tag.v
../../rtl/or1200/rtl/verilog/or1200_ic_fsm.v
../../rtl/or1200/rtl/verilog/or1200_spram_2048x8.v
../../rtl/or1200/rtl/verilog/or1200_spram_1024x8.v
../../rtl/or1200/rtl/verilog/or1200_ctrl.v
../../rtl/or1200/rtl/verilog/or1200_spram_64x14.v
../../rtl/or1200/rtl/verilog/or1200_qmem_top.v
../../rtl/or1200/rtl/verilog/or1200_dmmu_tlb.v
../../rtl/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
../../rtl/or1200/rtl/verilog/or1200_tt.v
../../rtl/or1200/rtl/verilog/or1200_immu_top.v
../../rtl/or1200/rtl/verilog/or1200_iwb_biu.v
../../rtl/or1200/rtl/verilog/or1200_spram_1024x32.v
../../rtl/or1200/rtl/verilog/or1200_spram_128x32.v
../../rtl/or1200/rtl/verilog/or1200_immu_tlb.v
../../rtl/or1200/rtl/verilog/or1200_operandmuxes.v
../../rtl/or1200/rtl/verilog/or1200_dc_top.v
../../rtl/or1200/rtl/verilog/or1200_sprs.v
../../rtl/or1200/rtl/verilog/or1200_sb.v
../../rtl/or1200/rtl/verilog/or1200_wbmux.v
../../rtl/or1200/rtl/verilog/or1200_spram_64x24.v
../../rtl/or1200/rtl/verilog/or1200_spram_512x20.v
../../rtl/or1200/rtl/verilog/or1200_du.v
../../rtl/or1200/rtl/verilog/or1200_if.v
../../rtl/or1200/rtl/verilog/or1200_ic_top.v
../../rtl/or1200/rtl/verilog/or1200_spram_2048x32.v
../../rtl/or1200/rtl/verilog/or1200_amultp2_32x32.v
../../rtl/or1200/rtl/verilog/or1200_spram_64x22.v
../../rtl/or1200/rtl/verilog/or1200_rf.v
../../rtl/or1200/rtl/verilog/or1200_top.v

../../rtl/ethernet/rtl/verilog/eth_defines.v
../../rtl/ethernet/rtl/verilog/eth_register.v
../../rtl/ethernet/rtl/verilog/eth_receivecontrol.v
../../rtl/ethernet/rtl/verilog/eth_fifo.v
../../rtl/ethernet/rtl/verilog/eth_miim.v
../../rtl/ethernet/rtl/verilog/xilinx_dist_ram_16x32.v
../../rtl/ethernet/rtl/verilog/eth_txstatem.v
../../rtl/ethernet/rtl/verilog/eth_registers.v
../../rtl/ethernet/rtl/verilog/eth_wishbone.v
../../rtl/ethernet/rtl/verilog/eth_random.v
../../rtl/ethernet/rtl/verilog/eth_crc.v
../../rtl/ethernet/rtl/verilog/eth_transmitcontrol.v
../../rtl/ethernet/rtl/verilog/eth_clockgen.v
../../rtl/ethernet/rtl/verilog/timescale.v
../../rtl/ethernet/rtl/verilog/eth_shiftreg.v
../../rtl/ethernet/rtl/verilog/eth_rxcounters.v
../../rtl/ethernet/rtl/verilog/eth_outputcontrol.v
../../rtl/ethernet/rtl/verilog/eth_maccontrol.v
../../rtl/ethernet/rtl/verilog/eth_rxaddrcheck.v
../../rtl/ethernet/rtl/verilog/eth_rxstatem.v
../../rtl/ethernet/rtl/verilog/eth_txethmac.v
../../rtl/ethernet/rtl/verilog/eth_spram_256x32.v
../../rtl/ethernet/rtl/verilog/eth_top.v
../../rtl/ethernet/rtl/verilog/eth_macstatus.v
../../rtl/ethernet/rtl/verilog/eth_cop.v
../../rtl/ethernet/rtl/verilog/eth_rxethmac.v
../../rtl/ethernet/rtl/verilog/eth_txcounters.v


-y ../../bench
-y ../../rtl/spi/rtl/verilog
-y ../../rtl/wb_conmax/rtl/verilog
-y ../../rtl/mem_if/rtl/verilog
-y ../../rtl/dbg_interface/rtl/verilog
-y ../../rtl
-y ../../rtl/rom_wb
-y ../../rtl/uart16550/rtl/verilog
-y ../../rtl/or1200/rtl/verilog
-y ../../rtl/ethernet/rtl/verilog