Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

../../bench/CPUboard_tb.v
../../bench/generic_pll/generic_pll.v
../../bench/models/512Kx8.v
../../bench/models/28f016s3/dp016s3.v
../../bench/models/28f016s3/bwsvff.v

../../rtl/wb_conmax/rtl/verilog/wb_conmax_master_if.v
../../rtl/wb_conmax/rtl/verilog/wb_conmax_defines.v
../../rtl/wb_conmax/rtl/verilog/wb_conmax_arb.v
../../rtl/wb_conmax/rtl/verilog/wb_conmax_pri_enc.v
../../rtl/wb_conmax/rtl/verilog/wb_conmax_top.v
../../rtl/wb_conmax/rtl/verilog/wb_conmax_msel.v
../../rtl/wb_conmax/rtl/verilog/wb_conmax_slave_if.v
../../rtl/wb_conmax/rtl/verilog/wb_conmax_rf.v
../../rtl/wb_conmax/rtl/verilog/wb_conmax_pri_dec.v

../../rtl/or1k_sco_top.v

../../rtl/rom_wb/rom_wb.v

../../rtl/mem_if/rtl/verilog/mc_wb_if.v
../../rtl/mem_if/rtl/verilog/mc_defines.v
../../rtl/mem_if/rtl/verilog/mc_top.v
../../rtl/mem_if/rtl/verilog/mc_cs_rf.v
../../rtl/mem_if/rtl/verilog/mc_dp.v
../../rtl/mem_if/rtl/verilog/mc_incn_r.v
../../rtl/mem_if/rtl/verilog/mc_timing.v
../../rtl/mem_if/rtl/verilog/mc_adr_sel.v
../../rtl/mem_if/rtl/verilog/mc_mem_if.v
../../rtl/mem_if/rtl/verilog/mc_obct.v
../../rtl/mem_if/rtl/verilog/mc_obct_top.v
../../rtl/mem_if/rtl/verilog/mc_refresh.v
../../rtl/mem_if/rtl/verilog/mc_rf.v
../../rtl/mem_if/rtl/verilog/mc_rd_fifo.v

../../rtl/or1200/rtl/verilog/or1200_reg2mem.v
../../rtl/or1200/rtl/verilog/or1200_dpram_32x32.v
../../rtl/or1200/rtl/verilog/or1200_wb_biu.v
../../rtl/or1200/rtl/verilog/or1200_pm.v
../../rtl/or1200/rtl/verilog/or1200_tpram_32x32.v
../../rtl/or1200/rtl/verilog/or1200_gmultp2_32x32.v
../../rtl/or1200/rtl/verilog/or1200_lsu.v
../../rtl/or1200/rtl/verilog/or1200_mem2reg.v
../../rtl/or1200/rtl/verilog/or1200_freeze.v
../../rtl/or1200/rtl/verilog/or1200_cfgr.v
../../rtl/or1200/rtl/verilog/or1200_defines.v
../../rtl/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
../../rtl/or1200/rtl/verilog/or1200_except.v
../../rtl/or1200/rtl/verilog/or1200_pic.v
../../rtl/or1200/rtl/verilog/or1200_dc_tag.v
../../rtl/or1200/rtl/verilog/or1200_rfram_generic.v
../../rtl/or1200/rtl/verilog/or1200_sb_fifo.v
../../rtl/or1200/rtl/verilog/or1200_dc_ram.v
../../rtl/or1200/rtl/verilog/timescale.v
../../rtl/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
../../rtl/or1200/rtl/verilog/or1200_dpram_256x32.v
../../rtl/or1200/rtl/verilog/or1200_cpu.v
../../rtl/or1200/rtl/verilog/or1200_ic_ram.v
../../rtl/or1200/rtl/verilog/or1200_dc_fsm.v
../../rtl/or1200/rtl/verilog/or1200_spram_32x24.v
../../rtl/or1200/rtl/verilog/or1200_mult_mac.v
../../rtl/or1200/rtl/verilog/or1200_spram_256x21.v
../../rtl/or1200/rtl/verilog/or1200_genpc.v
../../rtl/or1200/rtl/verilog/or1200_alu.v
../../rtl/or1200/rtl/verilog/or1200_dmmu_top.v
../../rtl/or1200/rtl/verilog/or1200_ic_tag.v
../../rtl/or1200/rtl/verilog/or1200_ic_fsm.v
../../rtl/or1200/rtl/verilog/or1200_spram_2048x8.v
../../rtl/or1200/rtl/verilog/or1200_spram_1024x8.v
../../rtl/or1200/rtl/verilog/or1200_ctrl.v
../../rtl/or1200/rtl/verilog/or1200_spram_64x14.v
../../rtl/or1200/rtl/verilog/or1200_qmem_top.v
../../rtl/or1200/rtl/verilog/or1200_dmmu_tlb.v
../../rtl/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
../../rtl/or1200/rtl/verilog/or1200_tt.v
../../rtl/or1200/rtl/verilog/or1200_immu_top.v
../../rtl/or1200/rtl/verilog/or1200_iwb_biu.v
../../rtl/or1200/rtl/verilog/or1200_spram_1024x32.v
../../rtl/or1200/rtl/verilog/or1200_spram_128x32.v
../../rtl/or1200/rtl/verilog/or1200_immu_tlb.v
../../rtl/or1200/rtl/verilog/or1200_operandmuxes.v
../../rtl/or1200/rtl/verilog/or1200_dc_top.v
../../rtl/or1200/rtl/verilog/or1200_sprs.v
../../rtl/or1200/rtl/verilog/or1200_sb.v
../../rtl/or1200/rtl/verilog/or1200_wbmux.v
../../rtl/or1200/rtl/verilog/or1200_spram_64x24.v
../../rtl/or1200/rtl/verilog/or1200_spram_512x20.v
../../rtl/or1200/rtl/verilog/or1200_du.v
../../rtl/or1200/rtl/verilog/or1200_if.v
../../rtl/or1200/rtl/verilog/or1200_ic_top.v
../../rtl/or1200/rtl/verilog/or1200_spram_2048x32.v
../../rtl/or1200/rtl/verilog/or1200_amultp2_32x32.v
../../rtl/or1200/rtl/verilog/or1200_spram_64x22.v
../../rtl/or1200/rtl/verilog/or1200_rf.v
../../rtl/or1200/rtl/verilog/or1200_top.v
../../rtl/flash_sram/flash_top.v
../../rtl/flash_sram/sram_top.v



-y ../../bench
-y ../../bench/models
-y ../../bench/models/28f016s3
-y ../../rtl/wb_conmax/rtl/verilog
-y ../../rtl
-y ../../rtl/rom_wb
-y ../../rtl/or1200/rtl/verilog
-y ../../rtl/flash_sram