OpenCores
URL https://opencores.org/ocsvn/or1k_soc_on_altera_embedded_dev_kit/or1k_soc_on_altera_embedded_dev_kit/trunk

Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [sim/] [bin/] [wave_signals.sav] - Rev 12

Compare with Previous | Blame | View Log

[size] 1440 877
[pos] 1279 28
*-26.260912 1413940000 1137979000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] CPUboard_tb.
[treeopen] CPUboard_tb.soc0.
[treeopen] CPUboard_tb.soc0.uart_top.
[treeopen] CPUboard_tb.soc0.uart_top.regs.
[treeopen] CPUboard_tb.soc0.uart_top.regs.transmitter.
@28
CPUboard_tb.clk
@200
-=====CPUBoard_tb=====
@28
CPUboard_tb.rstn
@200
-
@22
CPUboard_tb.gpio_pad_io[31:0]
@200
-===== SOC TOP =====
@28
CPUboard_tb.soc0.wb_clk_pad_i
CPUboard_tb.soc0.wb_rst_pad_i
CPUboard_tb.soc0.or1k_clmode_i[1:0]
@22
CPUboard_tb.soc0.pic_ints[19:0]
@200
-OR1k Instruction 
@28
CPUboard_tb.soc0.or1k_iwb_stb_o
CPUboard_tb.soc0.or1k_iwb_we_o
CPUboard_tb.soc0.or1k_iwb_cyc_o
CPUboard_tb.soc0.or1k_iwb_ack_i
@22
CPUboard_tb.soc0.or1k_iwb_sel_o[3:0]
CPUboard_tb.soc0.or1k_iwb_adr_o[31:0]
CPUboard_tb.soc0.or1k_iwb_dat_i[31:0]
CPUboard_tb.soc0.or1k_iwb_dat_o[31:0]
@28
CPUboard_tb.soc0.or1k_iwb_err_i
CPUboard_tb.soc0.or1k_iwb_rty_i
@200
-OR1k Data
@28
CPUboard_tb.soc0.or1k_dwb_stb_o
CPUboard_tb.soc0.or1k_dwb_we_o
CPUboard_tb.soc0.or1k_dwb_ack_i
CPUboard_tb.soc0.or1k_dwb_cyc_o
@22
CPUboard_tb.soc0.or1k_dwb_sel_o[3:0]
CPUboard_tb.soc0.or1k_dwb_adr_o[31:0]
CPUboard_tb.soc0.or1k_dwb_dat_i[31:0]
CPUboard_tb.soc0.or1k_dwb_dat_o[31:0]
@28
CPUboard_tb.soc0.or1k_dwb_err_i
CPUboard_tb.soc0.or1k_dwb_rty_i
@200
-
-=====Flash_top=====
@28
CPUboard_tb.soc0.flash_top.wb_clk_i
CPUboard_tb.soc0.flash_top.wb_rst_i
@22
CPUboard_tb.soc0.flash_top.a[20:0]
CPUboard_tb.soc0.flash_top.wb_sel_i[3:0]
@28
CPUboard_tb.soc0.flash_top.wb_stb_i
CPUboard_tb.soc0.flash_top.wb_cyc_i
CPUboard_tb.soc0.flash_top.wb_we_i
CPUboard_tb.soc0.flash_top.wb_ack_o
@22
CPUboard_tb.soc0.flash_top.wb_adr_i[31:0]
CPUboard_tb.soc0.flash_top.adr[31:0]
CPUboard_tb.soc0.flash_top.wb_dat_i[31:0]
CPUboard_tb.soc0.flash_top.wb_dat_o[31:0]
@28
CPUboard_tb.soc0.flash_top.a_oe
CPUboard_tb.soc0.flash_top.cen
@22
CPUboard_tb.soc0.flash_top.d[7:0]
@28
CPUboard_tb.soc0.flash_top.delay[1:0]
@22
CPUboard_tb.soc0.flash_top.fflash[31:0]
@28
CPUboard_tb.soc0.flash_top.flash_rstn
CPUboard_tb.soc0.flash_top.oen
CPUboard_tb.soc0.flash_top.rdy
CPUboard_tb.soc0.flash_top.wb_err
CPUboard_tb.soc0.flash_top.wb_err_o
CPUboard_tb.soc0.flash_top.wen
@200
-
-=====uart_top=====
@22
CPUboard_tb.soc0.wb_us_adr_i[31:0]
CPUboard_tb.soc0.wb_us_sel_i[3:0]
@28
CPUboard_tb.soc0.wb_us_stb_i
CPUboard_tb.soc0.wb_us_cyc_i
CPUboard_tb.soc0.wb_us_we_i
CPUboard_tb.soc0.wb_us_ack_o
@22
CPUboard_tb.soc0.wb_us_dat_i[31:0]
CPUboard_tb.soc0.wb_us_dat_o[31:0]
@200
-
@22
CPUboard_tb.soc0.uart_top.lcr[7:0]
CPUboard_tb.soc0.uart_top.lsr[7:0]
CPUboard_tb.soc0.uart_top.mcr[4:0]
CPUboard_tb.soc0.uart_top.msr[7:0]
@200
-
@22
CPUboard_tb.soc0.uart_top.wb_dat8_i[7:0]
@23
CPUboard_tb.soc0.uart_top.wb_dat8_o[7:0]
@22
CPUboard_tb.soc0.uart_top.regs.transmitter.fifo_tx.count[4:0]
CPUboard_tb.soc0.uart_top.regs.transmitter.fifo_tx.data_out[7:0]
@28
CPUboard_tb.soc0.uart_top.srx_pad_i
CPUboard_tb.soc0.uart_top.stx_pad_o
@200
-=====mem_if=====
@28
CPUboard_tb.soc0.mc_clk_pad_i
@22
CPUboard_tb.soc0.mem_if_wb_sel_i[3:0]
@28
CPUboard_tb.soc0.mem_if_wb_err_o
CPUboard_tb.soc0.mem_if_wb_stb_i
CPUboard_tb.soc0.mem_if_wb_cyc_i
CPUboard_tb.soc0.mem_if_wb_ack_o
@22
CPUboard_tb.soc0.mem_if_wb_addr_i[31:0]
CPUboard_tb.soc0.mem_if_wb_data_i[31:0]
CPUboard_tb.soc0.mem_if_wb_data_o[31:0]
@28
CPUboard_tb.soc0.mem_if_wb_we_i
@200
-
@22
CPUboard_tb.soc0.mem_adr_pad_o[12:0]
@28
CPUboard_tb.soc0.mem_dat_pad_oe
@22
CPUboard_tb.soc0.mem_dat_pad_i[31:0]
CPUboard_tb.soc0.mem_dat_pad_o[31:0]
CPUboard_tb.soc0.mem_dat_pad_io[31:0]
CPUboard_tb.soc0.mc_addr_wire_o[23:0]
@28
CPUboard_tb.soc0.mem_ba_pad_o[1:0]
CPUboard_tb.soc0.mem_cas_pad_o
CPUboard_tb.soc0.mem_cke_pad_o
CPUboard_tb.soc0.mem_con_pad_oe
CPUboard_tb.soc0.mem_cs_pad_o
@22
CPUboard_tb.soc0.mem_csi_pad_o[7:0]
CPUboard_tb.soc0.mem_dqm_pad_o[3:0]
@28
CPUboard_tb.soc0.mem_oe_pad_o_
CPUboard_tb.soc0.mem_ras_pad_o
CPUboard_tb.soc0.mem_we_pad_o
@200
-
@22
CPUboard_tb.mem_adr_pad_o[12:0]
@28
CPUboard_tb.mem_ba_pad_o[1:0]
CPUboard_tb.mem_cas_pad_o
CPUboard_tb.mem_cke_pad_o
CPUboard_tb.mem_cs_pad_o
@22
CPUboard_tb.mem_dat_pad_io[31:0]
CPUboard_tb.mem_dqm_pad_o[3:0]
@28
CPUboard_tb.mem_ras_pad_o
CPUboard_tb.mem_we_pad_o

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.