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https://opencores.org/ocsvn/pci/pci/trunk
Subversion Repositories pci
[/] [pci/] [tags/] [rel_00/] [rtl/] [verilog/] [KNOWN_ISSUES] - Rev 154
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Known issues for current RTL version:- PCI Bridge's WISHBONE Master doesn't work properly,when REGISTER_WBM_OUTPUTS is defined and WISHBONE Slave connected to itoperates with 0 wait cycles.