Subversion Repositories pci

//+ncelabargs+"-timescale 1ns/10ps"
+libext+.v
// RTL sources
../../../rtl/verilog/pci_parity_check.v
../../../rtl/verilog/pci_target_unit.v
../../../rtl/verilog/wb_addr_mux.v
../../../rtl/verilog/cbe_en_crit.v
../../../rtl/verilog/fifo_control.v
../../../rtl/verilog/out_reg.v
../../../rtl/verilog/pci_tpram.v
../../../rtl/verilog/wb_master.v
../../../rtl/verilog/conf_cyc_addr_dec.v
../../../rtl/verilog/frame_crit.v
../../../rtl/verilog/pci_target32_clk_en.v
../../../rtl/verilog/pciw_fifo_control.v
../../../rtl/verilog/wb_slave.v
../../../rtl/verilog/conf_space.v
../../../rtl/verilog/frame_en_crit.v
../../../rtl/verilog/par_crit.v
../../../rtl/verilog/pci_target32_ctrl_en_crit.v
../../../rtl/verilog/pciw_pcir_fifos.v
../../../rtl/verilog/wb_slave_unit.v
../../../rtl/verilog/frame_load_crit.v
../../../rtl/verilog/pci_bridge32.v
../../../rtl/verilog/pci_target32_devs_crit.v
../../../rtl/verilog/perr_crit.v
../../../rtl/verilog/wbr_fifo_control.v
../../../rtl/verilog/cur_out_reg.v
../../../rtl/verilog/pci_decoder.v
../../../rtl/verilog/pci_target32_interface.v
../../../rtl/verilog/perr_en_crit.v
../../../rtl/verilog/wbw_fifo_control.v
../../../rtl/verilog/decoder.v
../../../rtl/verilog/pci_in_reg.v
../../../rtl/verilog/pci_target32_load_crit.v
../../../rtl/verilog/serr_crit.v
../../../rtl/verilog/wbw_wbr_fifos.v
../../../rtl/verilog/delayed_sync.v
../../../rtl/verilog/irdy_out_crit.v
../../../rtl/verilog/pci_io_mux.v
../../../rtl/verilog/pci_io_mux_ad_en_crit.v
../../../rtl/verilog/pci_io_mux_ad_load_crit.v
../../../rtl/verilog/pci_target32_sm.v
../../../rtl/verilog/serr_en_crit.v
../../../rtl/verilog/delayed_write_reg.v
../../../rtl/verilog/mas_ad_en_crit.v
../../../rtl/verilog/mas_ad_load_crit.v
../../../rtl/verilog/pci_master32_sm.v
../../../rtl/verilog/pci_target32_stop_crit.v
../../../rtl/verilog/synchronizer_flop.v
../../../rtl/verilog/async_reset_flop.v
../../../rtl/verilog/mas_ch_state_crit.v
../../../rtl/verilog/pci_master32_sm_if.v
../../../rtl/verilog/pci_target32_trdy_crit.v
../../../rtl/verilog/top.v
../../../rtl/verilog/pci_rst_int.v
../../../rtl/verilog/sync_module.v
../../../rtl/verilog/wb_tpram.v
// Sim sources
../../../bench/verilog/wb_master32.v
../../../bench/verilog/wb_master_behavioral.v
../../../bench/verilog/system.v
../../../bench/verilog/pci_blue_arbiter.v
../../../bench/verilog/pci_bus_monitor.v
../../../bench/verilog/pci_behaviorial_device.v
../../../bench/verilog/pci_behaviorial_master.v
../../../bench/verilog/pci_behaviorial_target.v
../../../bench/verilog/wb_slave_behavioral.v
../../../bench/verilog/wb_bus_mon.v
../../../bench/verilog/wb_slave32.v
../../../bench/verilog/pci_behavioral_iack_target.v
../../../bench/verilog/pci_unsupported_commands_master.v
// Libs
//../../../../lib/xilinx/lib/unisims/RAMB4_S16_S16.v
//../../../../lib/xilinx/lib/glbl/glbl.v
../../../../lib/artisan/art_hsdp_256x40.v